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| PIC18CXX8 High-Performance Microcontrollers with CAN Module High Performance RISC CPU: * C-compiler optimized architecture instruction set * Linear program memory addressing to 32 Kbytes * Linear data memory addressing to 4 Kbytes Program Memory On-Chip Device EPROM (bytes) Off-Chip On-Chip RAM (bytes) Advanced Analog Features: * 10-bit Analog-to-Digital Converter module (A/D) with: - Fast sampling rate - Conversion available during SLEEP - DNL = 1 LSb, INL = 1 LSb - Up to 16 channels available * Analog Comparator Module: - 2 Comparators - Programmable input and output multiplexing * Comparator Voltage Reference Module * Programmable Low Voltage Detection (LVD) module - Supports interrupt on low voltage detection * Programmable Brown-out Reset (BOR) # Single Maximum Word Addressing Instructions (bytes) PIC18C658 PIC18C858 32 K 32 K 16384 16384 N/A N/A 1536 1536 * Up to 10 MIPS operation: - DC - 40 MHz clock input - 4 MHz - 10 MHz osc./clock input with PLL active * 16-bit wide instructions, 8-bit wide data path * Priority levels for interrupts * 8 x 8 Single Cycle Hardware Multiplier CAN BUS Module Features: * Message bit rates up to 1 Mbps * Conforms to CAN 2.0B ACTIVE Spec with: - 29-bit Identifier Fields - 8 byte message length * 3 Transmit Message Buffers with prioritization * 2 Receive Message Buffers * 6 full 29-bit Acceptance Filters * Prioritization of Acceptance Filters * Multiple Receive Buffers for High Priority Messages to prevent loss due to overflow * Advanced Error Management Features Peripheral Features: * * * * * * * * * High current sink/source 25 mA/25 mA Up to 76 I/O with individual direction control Four external interrupt pins Timer0 module: 8-bit/16-bit timer/counter with 8-bit programmable prescaler Timer1 module: 16-bit timer/counter Timer2 module: 8-bit timer/counter with 8-bit period register (time base for PWM) Timer3 module: 16-bit timer/counter Secondary oscillator clock option - Timer1/Timer3 Two Capture/Compare/PWM (CCP) modules CCP pins can be configured as: - Capture input: 16-bit, max resolution 6.25 ns - Compare is 16-bit, max resolution 100 ns (TCY) - PWM output: PWM resolution is 1- to 10-bit. Max. PWM freq. @:8-bit resolution = 156 kHz 10-bit resolution = 39 kHz Master Synchronous Serial Port (MSSP) with two modes of operation: - 3-wire SPITM (Supports all 4 SPI modes) - I2CTM Master and Slave mode Addressable USART module: Supports Interrupt on Address bit Special Microcontroller Features: * Power-on Reset (POR), Power-up Timer (PWRT), and Oscillator Start-up Timer (OST) * Watchdog Timer (WDT) with its own on-chip RC oscillator * Programmable code protection * Power saving SLEEP mode * Selectable oscillator options, including: - 4X Phase Lock Loop (of primary oscillator) - Secondary Oscillator (32 kHz) clock input * In-Circuit Serial Programming (ICSPTM) via two pins * CMOS Technology: * * * * * Low power, high speed EPROM technology Fully static design Wide operating voltage range (2.5V to 5.5V) Industrial and Extended temperature ranges Low power consumption * 2000 Microchip Technology Inc. Advanced Information DS30475A-page 1 PIC18CXX8 Pin Diagrams 64-Pin TQFP RE5 RE6 RE7/CCP2 RD0/PSP0 VDD VSS RD1/PSP1 RD2/PSP2 RD3/PSP3 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE1/WR RE0/RD RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 MCLR/VPP RG4 VSS VDD RF7 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4 RB5 RB6 VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 PIC18C658 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 41 40 39 38 37 36 35 34 33 RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RE2/CS RE3 RE4 RA2/AN2/VREF- RA1/AN1 RA0/AN0 VSS VDD RA5/SS/AN4/LVDIN RF0/AN5 AVDD RF1/AN6/C2OUT AVSS RA3/AN3/VREF+ DS30475A-page 2 Advanced Information RA4/T0CKI RC1/T1OSI 2000 Microchip Technology Inc. PIC18CXX8 Pin Diagrams (Cont.'d) 68-Pin PLCC RE2/CS RE3 RE4 RE5 RE6 RE7/CCP2 RD0/PSP0 VDD NC VSS RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 RE1/WR RE0/RD RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 MCLR/VPP RG4 NC VSS VDD RF7 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4 RB5 RB6 VSS NC OSC2/CLKO/RA6 OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 PIC18C658 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 NC VSS 2000 Microchip Technology Inc. Advanced Information VDD RA5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT DS30475A-page 3 PIC18CXX8 Pin Diagrams (Cont.'d) 80-Pin TQFP RE5 RE6 RE7/CCP2 RD0/PSP0 VDD RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RH1 RH0 RE2/CS RE3 RE4 RD6/PSP6 RD7/PSP7 RJ0 RJ1 60 59 58 57 56 55 54 53 52 51 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RH2 RH3 RE1/WR RE0/RD RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 MCLR/VPP RG4 VSS VDD RF7 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RH7/AN15 RH6/AN14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RJ2 RJ3 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4 RB5 RB6 VSS OSC2/CLKO/RA6 OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RK3 RK2 PIC18C858 VSS 49 48 47 46 45 44 43 42 41 RF1/AN6/C2OUT RF0/AN5 RA4/T0CKI RC1/T1OSI DS30475A-page 4 Advanced Information RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RA2/AN2/VREF- RA5/SS/AN4/LVDIN AVSS RA3/AN3/VREF+ RH5/AN13 RH4/AN12 AVDD RA1/AN1 RA0/AN0 VSS RK0 RK1 VDD 2000 Microchip Technology Inc. PIC18CXX8 Pin Diagrams (Cont.'d) 84-Pin PLCC RH1 RH0 RE2/CS RE3 RE4 RE5 RE6 RE7/CCP2 RD0/PSP0 VDD NC VSS RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 RJ0 RJ1 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 RH2 RH3 RE1/WR RE0/RD RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 MCLR/VPP RG4 NC VSS VDD RF7 RF6/AN11 RF5/AN10/CVREF RF4/AN9 RF3/AN8 RF2/AN7/C1OUT RH7/AN15 RH6/AN14 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 RJ2 RJ3 RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4 RB5 RB6 VSS NC OSC2/CLKO/RA6 OSC1/CLKI VDD RB7 RC5/SDO RC4/SDI/SDA RC3/SCK/SCL RC2/CCP1 RK3 RK2 PIC18C858 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 2000 Microchip Technology Inc. RH5/AN13 RH4/AN12 RF1/AN6/C2OUT RF0/AN5 AVDD AVSS RA3/AN3/VREF+ RA2/AN2/VREFRA1/AN1 RA0/AN0 NC VSS VDD RA5/SS/AN4/LVDIN RA4/T0CKI RC1/T1OSI RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT RK0 Advanced Information RK1 DS30475A-page 5 PIC18CXX8 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Oscillator Configurations ............................................................................................................................................................ 21 3.0 Reset .......................................................................................................................................................................................... 29 4.0 Memory Organization ................................................................................................................................................................. 41 5.0 Table Reads/Table Writes .......................................................................................................................................................... 65 6.0 8 X 8 Hardware Multiplier ........................................................................................................................................................... 71 7.0 Interrupts .................................................................................................................................................................................... 75 8.0 I/O Ports ..................................................................................................................................................................................... 89 9.0 Parallel Slave Port .................................................................................................................................................................... 109 10.0 Timer0 Module ......................................................................................................................................................................... 113 11.0 Timer1 Module ......................................................................................................................................................................... 117 12.0 Timer2 Module ......................................................................................................................................................................... 121 13.0 Timer3 Module ......................................................................................................................................................................... 123 14.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 127 15.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 135 16.0 Addressable Universal Synchronous Asynchronous Receiver Transmitter (USART).............................................................. 167 17.0 CAN Module ............................................................................................................................................................................. 183 18.0 10-bit Analog-to-Digital Converter (A/D) Module ...................................................................................................................... 227 19.0 Comparator Module.................................................................................................................................................................. 237 20.0 Comparator Voltage Reference Module ................................................................................................................................... 243 21.0 Low Voltage Detect .................................................................................................................................................................. 247 22.0 Special Features of the CPU .................................................................................................................................................... 251 23.0 Instruction Set Summary .......................................................................................................................................................... 261 24.0 Development Support............................................................................................................................................................... 305 25.0 Electrical Characteristics .......................................................................................................................................................... 311 26.0 DC and AC Characteristics Graphs and Tables ....................................................................................................................... 341 27.0 Packaging Information.............................................................................................................................................................. 343 Appendix A: Data Sheet Revision History ...................................................................................................................................... 349 Appendix B: Device Differences..................................................................................................................................................... 349 Appendix C: Device Migrations ...................................................................................................................................................... 350 Appendix D: Migrating from other PICmicro Devices ..................................................................................................................... 350 Appendix E: Development Tool Version Requirements ................................................................................................................. 351 Index .................................................................................................................................................................................................. 353 On-Line Support................................................................................................................................................................................. 361 Reader Response .............................................................................................................................................................................. 362 PIC18CXX8 Product Identification System ........................................................................................................................................ 363 DS30475A-page 6 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@mail.microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 7924150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) * The Microchip Corporate Literature Center; U.S. FAX: (480) 792-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 7 PIC18CXX8 NOTES: DS30475A-page 8 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 1.0 DEVICE OVERVIEW This document contains device specific information for the following three devices: 1. 2. PIC18C658 PIC18C858 The following two figures are device block diagrams sorted by pin count; 64/68-pin for Figure 1-1 and 80/84-pin for Figure 1-2. The 64/68-pin and 80/84-pin pinouts are listed in Table 1-2. The PIC18C658 is available in 64-pin TQFP and 68-pin PLCC packages. The PIC18C858 is available in 80-pin TQFP and 84-pin PLCC packages. An overview of features is shown in Table 1-1. TABLE 1-1: DEVICE FEATURES Features PIC18C658 DC - 40 MHz Bytes 32 K 16384 1536 21 Ports A - G 4 2 MSSP, CAN Addressable USART PSP 12 input channels 2 # of Single word Instructions PIC18C858 DC - 40 MHz 32 K 16384 1536 21 Ports A - H, J, K 4 2 MSSP, CAN Addressable USART PSP 16 input channels 2 Operating Frequency Program Memory Internal Data Memory (Bytes) Interrupt sources I/O Ports Timers Capture/Compare/PWM modules Serial Communications Parallel Communications 10-bit Analog-to-Digital Module Analog Comparators RESETS (and Delays) Programmable Low Voltage Detect Programmable Brown-out Reset CAN Module In-Circuit Serial Programming (ICSPTM) Instruction Set Packages POR, BOR, POR, BOR, RESET Instruction, Stack Full, RESET Instruction, Stack Full, Stack Underflow Stack Underflow (PWRT, OST) (PWRT, OST) Yes Yes Yes Yes 75 Instructions 64-pin TQFP 68-pin CERQUAD (Windowed) 68-pin PLCC Yes Yes Yes Yes 75 Instructions 80-pin TQFP 84-pin CERQUAD (Windowed) 84-pin PLCC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 9 PIC18CXX8 FIGURE 1-1: PIC18C658 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB7:RB4 PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD 8 RD7/PSP7:RD0/PSP0 PRODH PRODL Instruction Decode & Control Power-up Timer Timing Generation Oscillator Start-up Timer Power-on Reset Precision Bandgap Reference Watchdog Timer Brown-out Reset PORTE 8 x 8 Multiply 3 BITOP 8 WREG 8 8 ALU<8> 8 PORTF RF7 RF6/AN11:RF0/AN5 PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 RG4 8 8 RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 RE7/CCP2 21 21 Table Pointer<21> 8 inc/dec logic 8 Data Latch Data RAM ( 1.5 K ) Address Latch 20 PCLATU PCLATH 12 Address<12> 4 BSR PCU PCH PCL Program Counter Address Latch Program Memory (32 Kbytes) Data Latch 31 Level Stack 12 FSR0 FSR1 FSR2 inc/dec logic 4 Bank0, F 12 Decode TABLELATCH 16 8 ROMLATCH IR OSC2/CLKO OSC1/CLKI MCLR VDD, VSS BOR LVD Timer0 Timer1 Timer2 Timer3 10-bit ADC Comparator CCP1 CCP2 Synchronous Serial Port USART CAN Module DS30475A-page 10 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 1-2: PIC18C858 BLOCK DIAGRAM Data Bus<8> PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS/LVDIN RA6 PORTB RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB7:RB4 PORTC RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTD 8 RD7/PSP7:RD0/PSP0 PRODH PRODL Instruction Decode & Control Power-up Timer Timing Generation Oscillator Start-up Timer Power-on Reset Precision Bandgap Reference Watchdog Timer Brown-out Reset PORTE 8 x 8 Multiply 3 BITOP 8 WREG 8 8 ALU<8> 8 PORTF RF7 RF6/AN11:RF0/AN5 PORTG RG0/CANTX1 RG1/CANTX2 RG2/CANRX RG3 RG4 8 8 RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 RE7 21 21 Table Pointer<21> 8 inc/dec logic 8 Data Latch Data RAM ( 1.5 K ) Address Latch 20 PCLATU PCLATH 12 Address<12> 4 BSR PCU PCH PCL Program Counter Address Latch Program Memory (32 Kbytes) Data Latch 31 Level Stack 12 FSR0 FSR1 FSR2 inc/dec logic 4 Bank0, F 12 Decode TABLELATCH 16 8 ROMLATCH IR OSC2/CLKO OSC1/CLKI MCLR VDD, VSS PORTK RK0 RK1 RK2 RK3 PORTJ RJ0 RJ1 RJ2 RJ3 PORTH RH0 RH1 RH2 RH3 RH7/AN15:RH4/AN12 BOR LVD Timer0 Timer1 Timer2 Timer3 10-bit ADC Comparator CCP1 CCP2 Synchronous Serial Port USART CAN Module 2000 Microchip Technology Inc. Advanced Information DS30475A-page 11 PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS Pin Number Pin Name PIC18C658 TQFP MCLR/VPP MCLR VPP NC OSC1/CLKI OSC1 -- 39 1, 18, 35, 52 50 -- 49 1, 22, 43, 64 62 I CMOS/ST Oscillator crystal input or external clock source input. ST buffer when configured in RC mode. Otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). 7 PLCC 16 PIC18C858 TQFP 9 PLCC 20 I P -- ST Master clear (RESET) input. This pin is an active low RESET to the device. Programming voltage input These pins should be left unconnected Pin Type Buffer Type Description -- CLKI I CMOS OSC2/CLKO/RA6 OSC2 40 51 50 63 Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. O -- In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate I/O TTL General purpose I/O pin CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) O -- CLKO RA6 Legend: TTL ST I P = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS30475A-page 12 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RA0/AN0 RA0 AN0 RA1/AN1 RA1 AN1 RA2/AN2/VREFRA2 AN2 VREFRA3/AN3/VREF+ RA3 AN3 VREF+ RA4/T0CKI RA4 24 PLCC 34 PIC18C858 TQFP 30 PLCC 42 I/O I 23 33 29 41 I/O I 22 32 28 40 I/O I I 21 31 27 39 I/O I I 28 39 34 47 I/O I I/O I I I ST/OD ST TTL Analog ST Analog = = = = Digital I/O - Open drain when configured as output Timer0 external clock input TTL Analog Analog Digital I/O Analog input 3 A/D reference voltage (High) input TTL Analog Analog Digital I/O Analog input 2 A/D reference voltage (Low) input TTL Analog Digital I/O Analog input 1 TTL Analog Digital I/O Analog input 0 Pin Type Buffer Type Description PORTA is a bi-directional I/O port T0CKI 27 38 33 46 RA5/AN4/SS/LVDIN RA5 AN4 SS LVDIN RA6 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power CMOS Analog O OD Digital I/O Analog input 4 SPI slave select input Low voltage detect input See the OSC2/CLKO/RA6 pin CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 13 PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC PIC18C858 TQFP PLCC Pin Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT0 RB0 INT0 RB1/INT1 RB1 INT1 RB2/INT2 RB2 INT2 RB3/INT3 RB3 INT3 RB4 RB5 RB6 48 60 58 72 I/O I 47 59 57 71 I/O I 46 58 56 70 I/O I 45 57 55 69 I/O I/O I/O Digital I/O External interrupt 3 Digital I/O Interrupt on change pin I/O TTL Digital I/O Interrupt-on-change pin I/O TTL Digital I/O Interrupt-on-change pin I ST ICSP programming clock I/O TTL Digital I/O Interrupt-on-change pin I/O ST ICSP programming data CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) TTL ST TTL TTL ST Digital I/O External interrupt 2 TTL ST Digital I/O External interrupt 1 TTL ST Digital I/O External interrupt 0 44 43 42 56 55 54 54 53 52 68 67 66 RB7 37 48 47 60 Legend: TTL ST I P = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS30475A-page 14 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RC0/T1OSO/T13CKI RC0 T1OSO T13CKI RC1/T1OSI RC1 T1OSI RC2/CCP1 RC2 CCP1 RC3/SCK/SCL RC3 SCK SCL RC4/SDI/SDA RC4 SDI SDA RC5/SDO RC5 SDO RC6/TX/CK RC6 TX CK RC7/RX/DT RC7 RX DT Legend: TTL ST I P = = = = 35 46 45 58 I/O I I/O 36 47 46 59 I/O O 31 42 37 50 I/O O I/O 32 43 38 51 I/O I I/O TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD ST ST ST = = = = Digital I/O USART asynchronous receive USART synchronous data (See TX/CK) CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) ST -- ST Digital I/O USART asynchronous transmit USART synchronous clock (See RX/DT) ST -- Digital I/O SPI data out ST ST ST Digital I/O SPI data in I2C data I/O 30 PLCC 41 PIC18C858 TQFP 36 PLCC 49 I/O O I 29 40 35 48 I/O I 33 44 43 56 I/O I/O 34 45 44 57 I/O I/O I/O ST ST ST Digital I/O Synchronous serial clock input/output for SPI mode Synchronous serial clock input/output for I2C mode ST ST Digital I/O Capture1 input/Compare1 output/PWM1 output ST CMOS Digital I/O Timer1 oscillator input ST -- ST Digital I/O Timer1 oscillator output Timer1/Timer3 external clock input Pin Type Buffer Type Description PORTC is a bi-directional I/O port 2000 Microchip Technology Inc. Advanced Information DS30475A-page 15 PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP PLCC PIC18C858 TQFP PLCC Pin Type Buffer Type Description PORTD is a bi-directional I/O port. These pins have TTL input buffers when external memory is enabled. RD0/PSP0 RD0 PSP0 RD1/PSP1 RD1 PSP1 RD2/PSP2 RD2 PSP2 RD3/PSP3 RD3 PSP3 RD4/PSP4 RD4 PSP4 RD5/PSP5 RD5 PSP5 RD6/PSP6 RD6 PSP6 RD7/PSP7 RD7 PSP7 Legend: TTL ST I P 58 3 72 3 I/O I/O 55 67 69 83 I/O I/O 54 66 68 82 I/O I/O 53 65 67 81 I/O I/O 52 64 66 80 I/O I/O 51 63 65 79 I/O I/O 50 62 64 78 I/O I/O 49 61 63 77 I/O ST Digital I/O I/O TTL Parallel slave port data CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data ST TTL Digital I/O Parallel slave port data = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power DS30475A-page 16 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RE0/RD RE0 RD RE1/WR RE1 WR RE2/CS RE2 CS RE3 RE4 RE5 RE6 RE7/CCP2 RE7 CCP2 Legend: TTL ST I P = = = = 2 PLCC 11 PIC18C858 TQFP 4 PLCC 15 I/O I 1 10 3 14 I/O I 64 9 78 9 I/O I 63 62 61 60 59 8 7 6 5 4 77 76 75 74 73 8 7 6 5 4 I/O I/O I/O I/O I/O I/O TTL compatible input Schmitt Trigger input with CMOS levels Input Power CMOS Analog O OD ST TTL ST ST ST ST ST ST = = = = Digital I/O Chip select control for parallel slave port (See RD and WR) Digital I/O Digital I/O Digital I/O Digital I/O ST TTL Digital I/O Write control for parallel slave port (See CS and RD pins) ST TTL Digital I/O Read control for parallel slave port (See WR and CS pins) Pin Type Buffer Type Description PORTE is a bi-directional I/O port Digital I/O Capture2 input, Compare2 output, PWM2 output CMOS compatible input or output Analog input Output Open Drain (no P diode to VDD) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 17 PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RF0/AN5 RF0 AN5 18 PLCC 28 PIC18C858 TQFP 24 PLCC 36 I/O I I/O I O I/O I O I/O I I/O I I/O I O ST Analog ST Analog ST ST Analog ST ST Analog ST Analog ST Analog Analog Digital I/O Analog input 5 Digital I/O Analog input 6 Comparator 2 output Digital I/O Analog input 7 Comparator 1 output Digital I/O Analog input 8 Digital I/O Analog input 9 Digital I/O Analog input 10 Comparator VREF output Pin Type Buffer Type Description PORTF is a bi-directional I/O port RF1/AN6/C2OUT 17 27 23 35 RF1 AN6 C2OUT RF2/AN7/C1OUT 16 26 18 30 RF2 AN7 C1OUT RF3/AN8 15 25 17 29 RF1 AN8 RF4/AN9 14 24 16 28 RF1 AN9 RF5/AN10/CVREF 13 23 15 27 RF1 AN10 CVREF RF6/AN11 12 22 14 26 RF6 AN11 RF7 11 21 13 25 Legend: TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I = Input P = Power I/O ST Digital I/O I Analog Analog input 11 I/O ST Digital I/O CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) DS30475A-page 18 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RG0/CANTX1 RG0 CANTX1 RG1/CANTX2 RG1 CANTX2 RG2/CANRX RG2 CANRX RG3 RG4 RH0 RH1 RH2 RH3 RH4/AN12 RH4 AN12 RH5/AN13 RH5 AN13 RH6/AN14 RH6 AN14 RH7/AN15 RH7 AN15 Legend: TTL ST I P 3 PLCC 12 PIC18C858 TQFP 5 PLCC 16 I/O O 4 13 6 17 I/O O 5 14 7 18 I/O I I/O I/O I/O I/O I/O I/O I/O I -- -- 21 33 I/O I -- -- 20 32 I/O I -- -- 19 31 I/O ST Digital I/O I Analog Analog input 15 CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open Drain (no P diode to VDD) ST Analog Digital I/O Analog input 14 ST Analog Digital I/O Analog input 13 ST CAN Bus ST ST ST ST ST ST ST Analog Digital I/O CAN bus input Digital I/O Digital I/O PORTH is a bi-directional I/O port. Digital I/O Digital I/O Digital I/O Digital I/O Digital I/O Analog input 12 ST CAN Bus Digital I/O Complimentary CAN bus output or CAN bus bit time clock ST CAN Bus Digital I/O CAN bus output Pin Type Buffer Type Description PORTG is a bi-directional I/O port 6 8 -- -- -- -- -- 15 17 -- -- -- -- -- 8 10 79 80 1 2 22 19 21 10 11 12 13 34 = = = = TTL compatible input Schmitt Trigger input with CMOS levels Input Power 2000 Microchip Technology Inc. Advanced Information DS30475A-page 19 PIC18CXX8 TABLE 1-2: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name PIC18C658 TQFP RJ0 RJ0 RJ0 RJ1 RJ1 RJ1 RJ2 RJ2 RJ2 RJ3 RJ3 RJ3 RK0 RK1 RK2 RK3 VSS VDD AVSS AVDD Legend: -- -- 39 52 -- -- 40 53 -- -- 41 54 -- -- 42 55 9, 25, 19, 36, 11, 31, 23, 44, 41, 56 53, 68 51, 70 65, 84 10, 26, 2, 20, 12, 32, 2, 24, 38, 57 37, 49 48, 71 45, 61 20 30 26 38 19 29 25 37 TTL compatible input Schmitt Trigger input with CMOS levels Input Power -- -- -- -- 59 -- 73 -- I/O I/O I/O I/O I/O P P P P CMOS Analog O OD ST ST ST ST ST -- -- Digital I/O PORTK is a bi-directional I/O port Digital I/O Digital I/O Digital I/O Digital I/O Ground reference for logic and I/O pins Positive supply for logic and I/O pins -- -- -- -- 60 -- 74 -- I/O ST Digital I/O -- -- -- -- 61 -- 75 -- I/O ST Digital I/O -- -- PLCC -- -- PIC18C858 TQFP 62 -- PLCC 76 -- I/O ST Digital I/O Pin Type Buffer Type Description PORTJ is a bi-directional I/O port TTL ST I P = = = = -- Ground reference for analog modules -- Positive supply for analog modules = CMOS compatible input or output = Analog input = Output = Open Drain (no P diode to VDD) DS30475A-page 20 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 2.0 2.1 OSCILLATOR CONFIGURATIONS Oscillator Types FIGURE 2-1: CRYSTAL/CERAMIC RESONATOR OPERATION (HS, XT OR LP OSC CONFIGURATION) OSC1 To internal logic SLEEP The PIC18CXX8 can be operated in one of eight oscillator modes, programmable by three configuration bits (FOSC2, FOSC1, and FOSC0). 1. 2. 3. 4. 5. 6. 7. 8. LP XT HS HS4 RC RCIO EC ECIO Low Power Crystal Crystal/Resonator High Speed Crystal/Resonator High Speed Crystal/Resonator with PLL enabled External Resistor/Capacitor External Resistor/Capacitor with I/O pin enabled External Clock External Clock with I/O pin enabled C1(1) XTAL RS(2) C2(1) OSC2 RF(3) PIC18CXX8 Note 1: See Table 2-1 and Table 2-2 for recommended values of C1 and C2. 2: A series resistor (RS) may be required for AT strip cut crystals. 3: RF varies with the crystal chosen. 2.2 Crystal Oscillator/Ceramic Resonators In XT, LP, HS or HS4 (PLL) oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 2-1 shows the pin connections. An external clock source may also be connected to the OSC1 pin, as shown in Figure 2-3 and Figure 2-4. The PIC18CXX8 oscillator design requires the use of a parallel cut crystal. Note: Use of a series cut crystal may give a frequency out of the crystal manufacturer's specifications. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 21 PIC18CXX8 TABLE 2-1: CERAMIC RESONATORS Ranges Tested: Mode XT Freq 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz 20.0 MHz 25.0 MHz 4.0 MHz 8.0 MHz 10.0 MHz OSC1 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF TBD TBD TBD 10 - 68 pF TBD OSC2 68 - 100 pF 15 - 68 pF 15 - 68 pF 10 - 68 pF 10 - 22 pF TBD TBD TBD 10 - 68 pF TBD HS HS+PLL Note 1: Recommended values of C1 and C2 are identical to the ranges tested (Table 2-1). 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. These values are for design guidance only. See notes on this page. Resonators Used: 455 kHz 2.0 MHz 4.0 MHz 8.0 MHz 16.0 MHz Panasonic EFO-A455K04B Murata Erie CSA2.00MG Murata Erie CSA4.00MG Murata Erie CSA8.00MT Murata Erie CSA16.00MX 0.3% 0.5% 0.5% 0.5% 0.5% All resonators used did not have built-in capacitors. TABLE 2-2: Osc Type LP XT CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq 32.0 kHz 200 kHz 200 kHz 1.0 MHz 4.0 MHz Cap. Range C1 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF 15-33 pF TBD Cap. Range C2 33 pF 15 pF 47-68 pF 15 pF 15 pF 15 pF 15-33 pF 15-33 pF TBD 15 pF 15-33 pF TBD HS 4.0 MHz 8.0 MHz 20.0 MHz 25.0 MHz HS+PLL 4.0 MHz 8.0 MHz 10.0 MHz These values are for design guidance only. See notes on this page. Crystals Used 32.0 kHz 200 kHz 1.0 MHz 4.0 MHz 8.0 MHz 20.0 MHz Epson C-001R32.768K-A STD XTL 200.000KHz ECS ECS-10-13-1 ECS ECS-40-20-1 EPSON CA-301 8.000M-C EPSON CA-301 20.000M-C 20 PPM 20 PPM 50 PPM 50 PPM 30 PPM 30 PPM DS30475A-page 22 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 2.3 RC Oscillator 2.4 External Clock Input For timing insensitive applications, the "RC" and "RCIO" device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal process parameter variation. Furthermore, the difference in lead frame capacitance between package types will also affect the oscillation frequency, especially for low CEXT values. The user also needs to take into account variation due to tolerance of external R and C components used. Figure 2-2 shows how the R/C combination is connected. In the RC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. The EC and ECIO oscillator modes require an external clock source to be connected to the OSC1 pin. The feedback device between OSC1 and OSC2 is turned off in these modes to save current. There is no oscillator start-up time required after a Power-on Reset or after a recovery from SLEEP mode. In the EC oscillator mode, the oscillator frequency divided by 4 is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 2-3 shows the pin connections for the EC oscillator mode. FIGURE 2-3: EXTERNAL CLOCK INPUT OPERATION (EC OSC CONFIGURATION) OSC1 FIGURE 2-2: VDD REXT RC OSCILLATOR MODE Clock from ext. system FOSC/4 PIC18CXX8 OSC2 OSC1 CEXT VSS FOSC/4 or I/O Recommended values: OSC2/CLKO/RA6 Internal clock PIC18CXX8 The ECIO oscillator mode functions like the EC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). Figure 2-4 shows the pin connections for the ECIO oscillator mode. FIGURE 2-4: 3 k REXT 100 k CEXT > 20pF Clock from ext. system EXTERNAL CLOCK INPUT OPERATION (ECIO CONFIGURATION) OSC1 The RCIO oscillator mode functions like the RC mode, except that the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6). PIC18CXX8 RA6 I/O (OSC2) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 23 PIC18CXX8 2.5 HS4 (PLL) A Phase Locked Loop circuit is provided as a programmable option for users that want to multiply the frequency of the incoming crystal oscillator signal by 4. For an input clock frequency of 10 MHz, the internal clock frequency will be multiplied to 40 MHz. This is useful for customers who are concerned with EMI due to high frequency crystals. The PLL can only be enabled when the oscillator configuration bits are programmed for HS mode. If they are programmed for any other mode, the PLL is not enabled and the system clock will come directly from OSC1. The PLL is one of the modes of the FOSC2:FOSC0 configuration bits. The oscillator mode is specified during device programming. A PLL lock timer is used to ensure that the PLL has locked before device execution starts. The PLL lock timer has a time-out referred to as TPLL. FIGURE 2-5: PLL BLOCK DIAGRAM FOSC2:FOSC0 = `110' OSC2 FIN Crystal Osc Phase Comparator Loop Filter FOUT VCO SYSCLK Divide by 4 MUX 2000 Microchip Technology Inc. OSC1 DS30475A-page 24 Advanced Information PIC18CXX8 2.6 Oscillator Switching Feature 2.6.1 SYSTEM CLOCK SWITCH BIT The PIC18CXX8 devices include a feature that allows the system clock source to be switched from the main oscillator to an alternate low frequency clock source. For the PIC18CXX8 devices, this alternate clock source is the Timer1 oscillator. If a low frequency crystal (32 kHz, for example) has been attached to the Timer1 oscillator pins and the Timer1 oscillator has been enabled, the device can switch to a low power execution mode. Figure 2-6 shows a block diagram of the system clock sources. The clock switching feature is enabled by programming the Oscillator Switching Enable (OSCSEN) bit in Configuration register CONFIG1H to a '0'. Clock switching is disabled in an erased device. See Section 9 for further details of the Timer1 oscillator. See Section 22.0 for Configuration Register details. The system clock source switching is performed under software control. The system clock switch bit, SCS (OSCCON register), controls the clock switching. When the SCS bit is '0', the system clock source comes from the main oscillator selected by the FOSC2:FOSC0 configuration bits. When the SCS bit is set, the system clock source will come from the Timer1 oscillator. The SCS bit is cleared on all forms of RESET. Note: The Timer1 oscillator must be enabled to switch the system clock source. The Timer1 oscillator is enabled by setting the T1OSCEN bit in the Timer1 control register (T1CON). If the Timer1 oscillator is not enabled, any write to the SCS bit will be ignored (SCS bit forced cleared) and the main oscillator will continue to be the system clock source. FIGURE 2-6: DEVICE CLOCK SOURCES PIC18CXX8 Main Oscillator OSC2 SLEEP OSC1 Timer 1 Oscillator T1OSO T1OSCEN Enable Oscillator Clock Source option for other modules Note: I/O pins have diode protection to VDD and VSS. 4 x PLL TOSC TT1P Tosc/4 TSCLK T1OSI Clock Source MUX REGISTER 2-1: OSCCON REGISTER U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-1 SCS bit 0 bit 7-1 bit 0 Unimplemented: Read as '0' SCS: System Clock Switch bit when OSCSEN configuration bit = '0' and T1OSCEN bit is set: 1 = Switch to Timer1 Oscillator/Clock pin 0 = Use primary Oscillator/Clock input pin when OSCSEN is clear or T1OSCEN is clear: bit is forced clear Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 25 PIC18CXX8 2.6.2 OSCILLATOR TRANSITIONS The PIC18CXX8 devices contain circuitry to prevent "glitches" when switching between oscillator sources. Essentially, the circuitry waits for eight rising edges of the clock source that the processor is switching to. This ensures that the new clock source is stable and that its pulse width will not be less than the shortest pulse width of the two clock sources. A timing diagram indicating the transition from the main oscillator to the Timer1 oscillator is shown in Figure 2-7. The Timer1 oscillator is assumed to be running all the time. After the SCS bit is set, the processor is frozen at the next occurring Q1 cycle. After eight synchronization cycles are counted from the Timer1 oscillator, operation resumes. No additional delays are required after the synchronization cycles. The sequence of events that takes place when switching from the Timer1 oscillator to the main oscillator will depend on the mode of the main oscillator. In addition to eight clock cycles of the main oscillator, additional delays may take place. If the main oscillator is configured for an external crystal (HS, XT, LP), the transition will take place after an oscillator start-up time (TOST) has occurred. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS, XT and LP modes is shown in Figure 2-8. FIGURE 2-7: TIMING DIAGRAM FOR TRANSITION FROM OSC1 TO TIMER1 OSCILLATOR Q1 Q2 Q3 Q4 Q1 TT1P 1 2 3 4 Tscs 5 6 7 8 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 T1OSI OSC1 TOSC Internal System Clock SCS (OSCCON<0>) Program Counter PC TDLY PC + 2 PC + 4 Note 1: Delay on internal system clock is eight oscillator cycles for synchronization. FIGURE 2-8: TIMING DIAGRAM FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS,XT,LP) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 TOST OSC2 Internal System Clock SCS (OSCCON<0>) TOSC 1 2 3 4 5 TSCS 6 7 8 Program Counter PC PC + 2 PC + 4 Note 1: TOST = 1024TOSC (drawing not to scale). DS30475A-page 26 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 If the main oscillator is configured for HS4 (PLL) mode, an oscillator start-up time (TOST) plus an additional PLL time-out (TPLL) will occur. The PLL time-out is typically 2 ms and allows the PLL to lock to the main oscillator frequency. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for HS4 mode is shown in Figure 2-9. If the main oscillator is configured in the RC, RCIO, EC or ECIO modes, there is no oscillator start-up time-out. Operation will resume after eight cycles of the main oscillator have been counted. A timing diagram indicating the transition from the Timer1 oscillator to the main oscillator for RC, RCIO, EC and ECIO modes is shown in Figure 2-10. FIGURE 2-9: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (HS WITH PLL) Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 TOST OSC2 PLL Clock Input Internal System Clock SCS (OSCCON<0>) Program Counter PC PC + 2 PC + 4 TOSC 1 2 3 TPLL TSCS 4 5 6 7 8 Note 1: TOST = 1024TOSC (drawing not to scale). FIGURE 2-10: TIMING FOR TRANSITION BETWEEN TIMER1 AND OSC1 (RC, EC) Q3 Q4 Q1 TT1P Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 T1OSI OSC1 OSC2 Internal System Clock SCS (OSCCON<0>) TOSC 1 2 3 4 5 6 7 8 TSCS Program Counter PC PC + 2 PC + 4 Note 1: RC oscillator mode assumed. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 27 PIC18CXX8 2.7 Effects of SLEEP Mode on the On-chip Oscillator 2.8 Power-up Delays Power up delays are controlled by two timers, so that no external RESET circuitry is required for most applications. The delays ensure that the device is kept in RESET until the device power supply and clock are stable. For additional information on RESET operation, see Section 3.0 RESET. The first timer is the Power-up Timer (PWRT), which optionally provides a fixed delay of TPWRT (parameter #33) on power-up only (POR and BOR). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. With the PLL enabled (HS4 oscillator mode), the time-out sequence following a Power-on Reset is different from other oscillator modes. The time-out sequence is as follows: the PWRT time-out is invoked after a POR time delay has expired, then the Oscillator Start-up Timer (OST) is invoked. However, this is still not a sufficient amount of time to allow the PLL to lock at high frequencies. The PWRT timer is used to provide an additional time-out. This time is called TPLL (parameter #7) to allow the PLL ample time to lock to the incoming clock frequency. When the device executes a SLEEP instruction, the on-chip clocks and oscillator are turned off and the device is held at the beginning of an instruction cycle (Q1 state). With the oscillator off, the OSC1 and OSC2 signals will stop oscillating. Since all the transistor switching currents have been removed, SLEEP mode achieves the lowest current consumption of the device (only leakage currents). Enabling any on-chip feature that will operate during SLEEP will increase the current consumed during SLEEP. The user can wake from SLEEP through external RESET, Watchdog Timer Reset or through an interrupt. TABLE 2-3: RC RCIO ECIO EC LP, XT, and HS Note: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC1 Pin OSC2 Pin OSC Mode Floating, external resistor should pull high At logic low Floating, external resistor should pull high Configured as PORTA, bit 6 Floating Configured as PORTA, bit 6 Floating At logic low Feedback inverter disabled, at quiescent Feedback inverter disabled, at quiescent voltage level voltage level See Table 3-1 in Section 3.0 RESET, for time-outs due to SLEEP and MCLR Reset. DS30475A-page 28 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 3.0 RESET The PIC18CXX8 differentiates between various kinds of RESET: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP Watchdog Timer (WDT) Reset (during normal operation) Programmable Brown-out Reset (PBOR) RESET Instruction Stack Full Reset Stack Underflow Reset state on Power-on Reset, MCLR, WDT Reset, Brown-out Reset, MCLR Reset during SLEEP and by the RESET instruction. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR are set or cleared differently in different RESET situations, as indicated in Table 3-2. These bits are used in software to determine the nature of the RESET. See Table 3-3 for a full description of the RESET states of all registers. A simplified block diagram of the on-chip RESET circuit is shown in Figure 3-1. The Enhanced MCU devices have a MCLR noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. A WDT Reset does not drive MCLR pin low. Most registers are unaffected by a RESET. Their status is unknown on POR and unchanged by all other RESETs. The other registers are forced to a "RESET" FIGURE 3-1: RESET Instruction Stack Pointer SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Stack Full/Underflow Reset External Reset MCLR WDT Module VDD Rise Detect VDD Brown-out Reset OST/PWRT OST SLEEP WDT Time-out Reset Power-on Reset BOREN S 10-bit Ripple Counter OSC1 PWRT On-chip RC OSC (1) 10-bit Ripple Counter Chip_Reset R Q Enable PWRT Enable OST (2) Note 1: 2: This is a separate oscillator from the RC oscillator of the CLKI pin. See Table 3-1 for time-out situations. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 29 PIC18CXX8 3.1 Power-on Reset (POR) 3.2 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when a VDD rise is detected. To take advantage of the POR circuitry, connect the MCLR pin directly (or through a resistor) to VDD. This will eliminate external RC components usually needed to create a Power-on Reset delay. A minimum rise rate for VDD is specified (parameter D004). For a slow rise time, see Figure 3-2. When the device starts normal operation (exits the RESET condition), device operating parameters (voltage, frequency, temperature,...) must be met to ensure operation. If these conditions are not met, the device must be held in RESET until the operating conditions are met. Brown-out Reset may be used to meet the voltage start-up condition. The Power-up Timer provides a fixed nominal time-out (parameter #33), only on power-up from the POR. The Power-up Timer operates on an internal RC oscillator. The chip is kept in RESET as long as the PWRT is active. The PWRT's time delay allows VDD to rise to an acceptable level. A configuration bit (PWRTEN in CONFIG2L register) is provided to enable/disable the PWRT. The power-up time delay will vary from chip to chip due to VDD, temperature and process variation. See DC parameter #33 for details. 3.3 Oscillator Start-up Timer (OST) FIGURE 3-2: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW VDD POWER-UP) VDD The Oscillator Start-up Timer (OST) provides 1024 oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and stabilized. The OST time-out is invoked only for XT, LP, HS and HS4 modes and only on Power-on Reset or wake-up from SLEEP. D R R1 MCLR C 3.4 PIC18CXX8 PLL Lock Time-out Note 1: External Power-on Reset circuit is required only if the VDD power-up slope is too slow. The diode D helps discharge the capacitor quickly when VDD powers down. 2: R < 40 k is recommended to make sure that the voltage drop across R does not violate the device's electrical specification. 3: R1 = 100 to 1 k will limit any current flowing into MCLR from external capacitor C in the event of MCLR/VPP pin breakdown due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). With the PLL enabled, the time-out sequence following a Power-on Reset is different from other oscillator modes. A portion of the Power-up Timer is used to provide a fixed time-out that is sufficient for the PLL to lock to the main oscillator frequency. This PLL lock time-out (TPLL) is typically 2 ms and follows the oscillator start-up time-out (OST). 3.5 Brown-out Reset (BOR) A configuration bit, BOREN, can disable (if clear/programmed) or enable (if set) the Brown-out Reset circuitry. If VDD falls below parameter D005 for greater than parameter #35, the brown-out situation resets the chip. A RESET may not occur if VDD falls below parameter D005 for less than parameter #35. The chip will remain in Brown-out Reset until VDD rises above BVDD. The Power-up Timer will then be invoked and will keep the chip in RESET an additional time delay (parameter #33). If VDD drops below BVDD while the Power-up Timer is running, the chip will go back into a Brown-out Reset and the Power-up Timer will be initialized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. DS30475A-page 30 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 3.6 Time-out Sequence On power-up, the time-out sequence is as follows: First, PWRT time-out is invoked after the POR time delay has expired, then OST is activated. The total time-out will vary based on oscillator configuration and the status of the PWRT. For example, in RC mode with the PWRT disabled, there will be no time-out at all. Figure 3-3, Figure 3-4, Figure 3-5, Figure 3-6 and Figure 3-7 depict time-out sequences on power-up. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the time-outs will expire. Bringing MCLR high will begin execution immediately (Figure 3-5). This is useful for testing purposes or to synchronize more than one PIC18CXX8 device operating in parallel. Table 3-2 shows the RESET conditions for some Special Function Registers, while Table 3-3 shows the RESET conditions for all registers. TABLE 3-1: TIME-OUT IN VARIOUS SITUATIONS Power-up(2) PWRTEN = 0 PWRTEN = 1 Brown-out(2) Wake-up from SLEEP or Oscillator Switch Oscillator Configuration HS with PLL enabled(1) 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms 72 ms + 1024Tosc + 2 ms 1024Tosc + 2 ms HS, XT, LP EC External RC 72 ms + 1024Tosc 72 ms 72 ms 1024Tosc -- -- 72 ms + 1024Tosc 72 ms 72 ms 1024Tosc -- -- Note 1: 2 ms = Nominal time required for the 4X PLL to lock. 2: 72 ms is the nominal power-up timer delay. REGISTER 3-1: RCON REGISTER BITS AND POSITIONS R/W-0 IPEN bit 7 R/W-0 LWRT U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-1 POR R/W-1 BOR bit 0 TABLE 3-2: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter 0000h 0000h 0000h 0000h 0000h 0000h 0000h PC + 2 0000h PC + 2(1) RCON Register 00-1 1100 00-u uuuu 0u-0 uuuu 0u-u uu11 0u-u uu11 00-u 10uu 0u-u 01uu uu-u 00uu 0u-1 11u0 uu-u 00uu RI 1 u 0 u u u u u 1 u TO 1 u u u u 1 0 0 1 0 PD 1 u u u u 0 1 0 1 0 POR 0 u u 1 1 u u u u u BOR 0 u u 1 1 u u u 0 u STKFUL u u u u 1 u u u u u STKUNF u u u 1 u u u u u u Condition Power-on Reset MCLR Reset during normal operation Software Reset during normal operation Stack Full Reset during normal operation Stack Underflow Reset during normal operation MCLR Reset during SLEEP WDT Reset WDT Wake-up Brown-out Reset Interrupt wake-up from SLEEP Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bits are set, the PC is loaded with the interrupt vector (0x000008h or 0x000018h). 2000 Microchip Technology Inc. Advanced Information DS30475A-page 31 PIC18CXX8 FIGURE 3-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 3-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30475A-page 32 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 3-6: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 0V 1V TDEADTIME FIGURE 3-7: TIME-OUT SEQUENCE ON POR W/ PLL ENABLED (MCLR TIED TO VDD) VDD MCLR IINTERNAL POR TPWRT PWRT TIME-OUT TOST TPLL OST TIME-OUT PLL TIME-OUT INTERNAL RESET TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 33 PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register TOSU 658 858 ---0 0000 ---0 0000 ---0 uuuu(3) TOSH 658 858 0000 0000 0000 0000 uuuu uuuu(3) TOSL 658 858 0000 0000 0000 0000 uuuu uuuu(3) STKPTR 658 858 00-0 0000 00-0 0000 uu-u uuuu(3) PCLATU 658 858 ---0 0000 ---0 0000 ---u uuuu PCLATH 658 858 0000 0000 0000 0000 uuuu uuuu PCL 658 858 0000 0000 0000 0000 PC + 2(2) TBLPTRU 658 858 --00 0000 --00 0000 --uu uuuu TBLPTRH 658 858 0000 0000 0000 0000 uuuu uuuu TBLPTRL 658 858 0000 0000 0000 0000 uuuu uuuu TABLAT 658 858 0000 0000 0000 0000 uuuu uuuu PRODH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PRODL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INTCON 658 858 0000 000x 0000 000u uuuu uuuu(1) INTCON2 658 858 1111 1111 1111 1111 uuuu uuuu(1) INTCON3 658 858 1100 0000 1100 0000 uuuu uuuu(1) INDF0 658 858 N/A N/A N/A POSTINC0 658 858 N/A N/A N/A POSTDEC0 658 858 N/A N/A N/A PREINC0 658 858 N/A N/A N/A PLUSW0 658 858 N/A N/A N/A FSR0H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR0L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu WREG 658 858 xxxx xxxx uuuu uuuu uuuu uuuu INDF1 658 858 N/A N/A N/A POSTINC1 658 858 N/A N/A N/A POSTDEC1 658 858 N/A N/A N/A PREINC1 658 858 N/A N/A N/A PLUSW1 658 858 N/A N/A N/A Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 34 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register FSR1H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR1L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu BSR 658 858 ---- 0000 ---- 0000 ---- uuuu INDF2 658 858 N/A N/A N/A POSTINC2 658 858 N/A N/A N/A POSTDEC2 658 858 N/A N/A N/A PREINC2 658 858 N/A N/A N/A PLUSW2 658 858 N/A N/A N/A FSR2H 658 858 ---- 0000 ---- 0000 ---- uuuu FSR2L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu STATUS 658 858 ---x xxxx ---u uuuu ---u uuuu TMR0H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TMR0L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu T0CON 658 858 1111 1111 1111 1111 uuuu uuuu OSCCON 658 858 ---- ---0 ---- ---0 ---- ---u LVDCON 658 858 --00 0101 --00 0101 --uu uuuu WDTCON 658 858 ---- ---0 ---- ---0 ---- ---u 658 858 00-1 11q0 00-1 qquu uu-u qquu RCON(4, 6) TMR1H 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TMR1L 658 858 xxxx xxxx uuuu uuuu uuuu uuuu T1CON 658 858 0-00 0000 u-uu uuuu u-uu uuuu TMR2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PR2 658 858 1111 1111 1111 1111 1111 1111 T2CON 658 858 -000 0000 -000 0000 -uuu uuuu SSPBUF 658 858 xxxx xxxx uuuu uuuu uuuu uuuu SSPADD 658 858 0000 0000 0000 0000 uuuu uuuu SSPSTAT 658 858 0000 0000 0000 0000 uuuu uuuu SSPCON1 658 858 0000 0000 0000 0000 uuuu uuuu SSPCON2 658 858 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 35 PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register ADRESH ADRESL ADCON0 ADCON1 ADCON2 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON CVRCON CMCON TMR3H TMR3L T3CON PSPCON SPBRG RCREG TXREG TXSTA RCSTA IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 Legend: Note 1: 2: 3: 4: 5: 6: 7: 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 --00 0000 --00 0000 --uu uuuu 658 858 --00 0000 --00 0000 --uu uuuu 658 858 0--- -000 0--- -000 u--- -uuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 --00 0000 --00 0000 --uu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 --00 0000 --00 0000 --uu uuuu 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 0000 0000 uuuu uuuu uuuu uuuu 658 858 0000 ---0000 ---uuuu ---658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 0000 -01x 0000 -01u uuuu -uuu 658 858 0000 000x 0000 000u uuuu uuuu 658 858 1111 1111 1111 1111 uuuu uuuu 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 -1-- 1111 -1-- 1111 -u-- uuuu 658 858 -0-- 0000 -0-- 0000 -u-- uuuu(1) 658 858 -0-- 0000 -0-- 0000 -u-- uuuu 658 858 1111 1111 1111 1111 uuuu uuuu 658 858 -111 1111 -111 1111 -uuu uuuu 658 858 0000 0000 0000 0000 uuuu uuuu(1) 658 858 -000 0000 -000 0000 -uuu uuuu(1) 658 858 0000 0000 0000 0000 uuuu uuuu 658 858 -000 0000 -000 0000 -uuu uuuu u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. See Table 3-2 for RESET value for specific condition. Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. The long write enable is only reset on a POR or MCLR. Available on PIC18C858 only. DS30475A-page 36 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register TRISJ(7) 858 1111 1111 1111 1111 uuuu uuuu (7) 858 1111 1111 1111 1111 uuuu uuuu TRISH TRISG 658 858 ---1 1111 ---1 1111 ---u uuuu TRISF 658 858 1111 1111 1111 1111 uuuu uuuu TRISE 658 858 1111 1111 1111 1111 uuuu uuuu TRISD 658 858 1111 1111 1111 1111 uuuu uuuu TRISC 658 858 1111 1111 1111 1111 uuuu uuuu TRISB 658 858 1111 1111 1111 1111 uuuu uuuu 658 858 -111 1111(5) -111 1111(5) -uuu uuuu(5) TRISA(5) LATJ(7) 858 xxxx xxxx uuuu uuuu uuuu uuuu (7) 858 xxxx xxxx uuuu uuuu uuuu uuuu LATH LATG 658 858 ---x xxxx ---u uuuu ---u uuuu LATF 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATE 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATD 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATC 658 858 xxxx xxxx uuuu uuuu uuuu uuuu LATB 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 -xxx xxxx(5) -uuu uuuu(5) -uuu uuuu(5) LATA(5) PORTJ(7) 858 xxxx xxxx uuuu uuuu uuuu uuuu 858 0000 xxxx 0000 uuuu uuuu uuuu PORTH(7) PORTG 658 858 ---x xxxx ---u uuuu ---u uuuu PORTF 658 858 x000 0000 u000 0000 uuuu uuuu PORTE 658 858 --00 xxxx uuuu u000 uuuu uuuu PORTD 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTC 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTB 658 858 xxxx xxxx uuuu uuuu uuuu uuuu 658 858 -x0x 0000(5) -u0u 0000(5) -uuu uuuu(5) PORTA(5) TRISK 658 858 1111 1111 1111 1111 uuuu uuuu LATK 658 858 xxxx xxxx uuuu uuuu uuuu uuuu PORTK 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXERRCNT 658 858 0000 0000 0000 0000 uuuu uuuu RXERRCNT 658 858 0000 0000 0000 0000 uuuu uuuu COMSTAT 658 858 0000 0000 0000 0000 uuuu uuuu CIOCON 658 858 1000 ---1000 ---uuuu ---BRGCON3 658 858 -0-- -000 -0-- -000 -u-- -uuu BRGCON2 658 858 0000 0000 0000 0000 uuuu uuuu BRGCON1 658 858 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 37 PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register CANCON 658 858 xxxx xxxuuuu uuuuuuu uuuCANSTAT 658 858 xxx- xxxuuu- uuuuuu- uuuRXB0D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0DLC 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu RXB0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0SIDL 658 858 xxxx x-xx uuuu u-uu uuuu u-uu RXB0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB0CON 658 858 000- 0000 000- 0000 uuu- uuuu RXB1D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1DLC 658 858 0xxx xxxx 0uuu uuuu uuuu uuuu RXB1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1SIDL 658 858 xxxx x0xx uuuu u0uu uuuu uuuu RXB1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXB1CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB0D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 38 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register TXB0D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB0CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB1D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB1CON 658 858 0000 0000 0000 0000 uuuu uuuu TXB2D7 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D6 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D5 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D4 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D3 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D2 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D1 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2D0 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2DLC 658 858 0x00 xxxx 0u00 uuuu uuuu uuuu TXB2EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2SIDL 658 858 xxx0 x0xx uuu0 u0uu uuuu uuuu TXB2SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu TXB2CON 658 858 0000 0000 0000 0000 uuuu uuuu RXM1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 39 PIC18CXX8 TABLE 3-3: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Applicable Devices Power-on Reset, Brown-out Reset MCLR Reset WDT Reset RESET Instruction Stack Resets Wake-up via WDT or Interrupt Register RXM1SIDL 658 858 xxx- --xx uuu- --uu uuu- --uu RXM1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXM0SIDL 658 858 xxx- --xx uuu- --uu uuu- --uu RXM0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF5SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF5SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF4SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF4SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF3SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF3SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF2SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF2SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF1SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF1SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDL 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0EIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu RXF0SIDL 658 858 xxx- x-xx uuu- u-uu uuu- u-uu RXF0SIDH 658 858 xxxx xxxx uuuu uuuu uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 4: See Table 3-2 for RESET value for specific condition. 5: Bit 6 of PORTA, LATA, and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read '0'. 6: The long write enable is only reset on a POR or MCLR. 7: Available on PIC18C858 only. DS30475A-page 40 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 4.0 MEMORY ORGANIZATION FIGURE 4-1: There are two memory blocks in Enhanced MCU devices. These memory blocks are: * Program Memory * Data Memory Each block has its own bus so that concurrent access can occur. PROGRAM MEMORY MAP AND STACK FOR PIC18C658/858 PC<20:0> 21 Stack Level 1 * * * 4.1 Program Memory Organization Stack Level 31 RESET Vector The PIC18CXX8 devices have a 21-bit program counter that is capable of addressing the 2 Mbyte program memory space. The reset vector address is at 0000h and the interrupt vector addresses are at 0008h and 0018h. Figure 4-1 shows the diagram for program memory map and stack for the PIC18C658 and PIC18C858. 4.1.1 INTERNAL PROGRAM MEMORY OPERATION 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h All devices have 32 Kbytes of internal EPROM program memory. This means that the PIC18CXX8 devices can store up to 16K of single word instructions. Accessing a location between the physically implemented memory and the 2 Mbyte address will cause a read of all '0's (a NOP instruction). 7FFFh 8000h Read '1' 1FFFFFh 2000 Microchip Technology Inc. Advanced Information DS30475A-page 41 User Memory Space On-chip Program Memory PIC18CXX8 4.2 Return Address Stack 4.2.2 RETURN STACK POINTER (STKPTR) The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC (Program Counter) is pushed onto the stack when a PUSH, CALL or RCALL instruction is executed, or an interrupt is acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction. PCLATU and PCLATH are not affected by any of the return instructions. The stack operates as a 31 word by 21-bit stack memory and a 5-bit stack pointer, with the stack pointer initialized to 00000b after all RESETs. There is no RAM associated with stack pointer 00000b. This is only a RESET value. During a CALL type instruction causing a push onto the stack, the stack pointer is first incremented and the RAM location pointed to by the stack pointer is written with the contents of the PC. During a RETURN type instruction causing a pop from the stack, the contents of the RAM location indicated by the STKPTR is transferred to the PC and then the stack pointer is decremented. The stack space is not part of either program or data space. The stack pointer is readable and writable, and the data on the top of the stack is readable and writable through SFR registers. Status bits indicate if the stack pointer is at or beyond the 31 levels provided. 4.2.1 TOP-OF-STACK ACCESS The STKPTR register contains the stack pointer value, the STKFUL (stack full) status bit, and the STKUNF (stack underflow) status bits. Register 4-1 shows the STKPTR register. The value of the stack pointer can be 0 through 31. The stack pointer increments when values are pushed onto the stack and decrements when values are popped off the stack. At RESET, the stack pointer value will be 0. The user may read and write the stack pointer value. This feature can be used by a Real Time Operating System for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit can only be cleared in software or by a POR. The action that takes place when the stack becomes full depends on the state of the STVREN (stack overflow RESET enable) configuration bit. Refer to Section 18 for a description of the device configuration bits. If STVREN is set (default) the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit, and reset the device. The STKFUL bit will remain set and the stack pointer will be set to 0. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the stack pointer will increment to 31. The 32nd push will overwrite the 31st push (and so on), while STKPTR remains at 31. When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the stack pointer remains at 0. The STKUNF bit will remain set until cleared in software or a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the RESET vector, where the stack conditions can be verified and appropriate actions can be taken. The top of the stack is readable and writable. Three register locations, TOSU, TOSH and TOSL allow access to the contents of the stack location indicated by the STKPTR register. This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt, the software can read the pushed value by reading the TOSU, TOSH and TOSL registers. These values can be placed on a user defined software stack. At return time, the software can replace the TOSU, TOSH and TOSL and do a return. The user should disable the global interrupt enable bits during this time to prevent inadvertent stack operations. DS30475A-page 42 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 4-1: STKPTR - STACK POINTER REGISTER R/C-0 STKFUL bit 7 bit 7 STKFUL: Stack Full Flag bit 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as '0' SP4:SP0: Stack Pointer Location bits Note: Legend R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared C = Clearable bit Bit 7 and bit 6 can only be cleared in user software or by a POR. R/C-0 STKUNF U-0 -- R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 bit 6 bit 5 bit 4-0 FIGURE 4-2: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 TOSU 0x00 TOSH 0x1A TOSL 0x34 STKPTR<4:0> 00010 00011 Top-of-Stack 0x001A34 00010 0x000D58 00001 0x000000 00000(1) Note 1: No RAM associated with this address; always maintained `0's. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 43 PIC18CXX8 4.2.3 PUSH AND POP INSTRUCTIONS 4.3 Fast Register Stack Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable option. To push the current PC value onto the stack, a PUSH instruction can be executed. This will increment the stack pointer and load the current PC value onto the stack. TOSU, TOSH and TOSL can then be modified to place a return address on the stack. The POP instruction discards the current TOS by decrementing the stack pointer. The previous value pushed onto the stack then becomes the TOS value. 4.2.4 STACK FULL/UNDERFLOW RESETS A "fast return" option is available for interrupts and calls. A fast register stack is provided for the STATUS, WREG and BSR registers and is only one layer in depth. The stack is not readable or writable and is loaded with the current value of the corresponding register when the processor vectors for an interrupt. The values in the fast register stack are then loaded back into the working registers if the fast return instruction is used to return from the interrupt. A low or high priority interrupt source will push values into the stack registers. If both low and high priority interrupts are enabled, the stack registers cannot be used reliably for low priority interrupts. If a high priority interrupt occurs while servicing a low priority interrupt, the stack register values stored by the low priority interrupt will be overwritten. If high priority interrupts are not disabled during low priority interrupts, users must save the key registers in software during a low priority interrupt. If no interrupts are used, the fast register stack can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the fast register stack for a subroutine call, a fast call instruction must be executed. Example 4-1 shows a source code example that uses the fast register stack. These RESETs are enabled by programming the STVREN configuration bit. When the STVREN bit is disabled, a full or underflow condition will set the appropriate STKFUL or STKUNF bit, but not cause a device RESET. When the STVREN bit is enabled, a full or underflow will set the appropriate STKFUL or STKUNF bit and then cause a device RESET. The STKFUL or STKUNF bits are only cleared by the user software or a POR. EXAMPLE 4-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK * * SUB1 * * * RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK DS30475A-page 44 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 4.4 PCL, PCLATH and PCLATU The program counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bits wide. The low byte is called the PCL register. This register is readable and writable. The high byte is called the PCH register. This register contains the PC<15:8> bits and is not directly readable or writable. Updates to the PCH register may be performed through the PCLATH register. The upper byte is called PCU. This register contains the PC<20:16> bits and is not directly readable or writable. Updates to the PCU register may be performed through the PCLATU register. The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the LSb of PCL is fixed to a value of '0'. The PC increments by 2 to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The contents of PCLATH and PCLATU will be transferred to the program counter by an operation that writes PCL. Similarly, the upper two bytes of the program counter will be transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (See Section 4.8.1). 4.5 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks, namely Q1, Q2, Q3 and Q4. Internally, the program counter (PC) is incremented every Q1, the instruction is fetched from the program memory and latched into the instruction register in Q4. The instruction is decoded and executed during the following Q1 through Q4. The clocks and instruction execution flow are shown in Figure 4-3. FIGURE 4-3: CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKOUT (RC mode) Internal phase clock PC Fetch INST (PC) Execute INST (PC-2) PC+2 PC+4 Fetch INST (PC+2) Execute INST (PC) Fetch INST (PC+4) Execute INST (PC+2) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 45 PIC18CXX8 4.6 Instruction Flow/Pipelining 4.7 Instructions in Program Memory An "Instruction Cycle" consists of four Q cycles (Q1, Q2, Q3 and Q4). The instruction fetch and execute are pipelined such that fetch takes one instruction cycle while decode and execute takes another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g., GOTO), two cycles are required to complete the instruction (Example 4-2). A fetch cycle begins with the program counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the "Instruction Register" (IR) in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). The program memory is addressed in bytes. Instructions are stored as two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSB = '0'). Figure 4-1 shows an example of how instruction words are stored in the program memory. To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read '0' (See Section 4.4). The CALL and GOTO instructions have an absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC<20:1>, which accesses the desired byte address in program memory. Instruction #2 in Figure 4-1 shows how the instruction "GOTO 000006h" is encoded in the program memory. Program branch instructions that encode a relative address offset operate in the same manner. The offset value stored in a branch instruction represents the number of single word instructions by which the PC will be offset. Section 23.0 provides further details of the instruction set. EXAMPLE 4-2: INSTRUCTION PIPELINE FLOW TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h 2. MOVWF PORTB 3. BRA SUB_1 4. BSF Fetch 1 PORTA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is "flushed" from the pipeline while the new instruction is being fetched and then executed. TABLE 4-1: -- MOVLW 055h GOTO 000006h INSTRUCTIONS IN PROGRAM MEMORY Opcode 0E55h EF03h, F000h Memory 55h 0Eh 03h EFh 00h F0h Address 000007h 000008h 000009h 00000Ah 00000Bh 00000Ch 00000Dh 00000Eh 00000Fh 000010h 000011h 000012h Instruction MOVFF 123h, 456h C123h, F456h 23h C1h 56h F4h -- DS30475A-page 46 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 4.7.1 TWO WORD INSTRUCTIONS 4.8.1 COMPUTED GOTO The PIC18CXX8 devices have 4 two word instructions: MOVFF, CALL, GOTO and LFSR. The second word of these instructions has the 4 MSB's set to 1's and is a special kind of NOP instruction. The lower 12 bits of the second word contain data to be used by the instruction. If the first word of the instruction is executed, the data in the second word is accessed. If the second word of the instruction is executed by itself (first word was skipped), it will execute as a NOP. This action is necessary when the two word instruction is preceded by a conditional instruction that changes the PC. A program example that demonstrates this concept is shown in Example 4-3. Refer to Section 19.0 for further details of the instruction set. A computed GOTO is accomplished by adding an offset to the program counter (ADDWF PCL). A lookup table can be formed with an ADDWF PCL instruction and a group of RETLW 0xnn instructions. WREG is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next instruction executed will be one of the RETLW 0xnn instructions that returns the value 0xnn to the calling function. The offset value (value in WREG) specifies the number of bytes that the program counter should advance. In this method, only one data byte may be stored in each instruction location and room on the return address stack is required. Warning: Lookup tables are implemented two ways. These are: * Computed GOTO * Table Reads The LSb of PCL is fixed to a value of `0'. Hence, computed GOTO to an odd address is not possible. 4.8 Lookup Tables 4.8.2 TABLE READS/TABLE WRITES A better method of storing data in program memory allows 2 bytes of data to be stored in each instruction location. Lookup table data may be stored as 2 bytes per program word by using table reads and writes. The table pointer (TBLPTR) specifies the byte address and the table latch (TABLAT) contains the data that is read from, or written to, program memory. Data is transferred to/from program memory one byte at a time. A description of the Table Read/Table Write operation is shown in Section 5.0. EXAMPLE 4-3: TWO WORD INSTRUCTIONS CASE 1: Source Code is RAM location 0? No, execute 2-word instruction 2nd operand holds address of REG2 continue code 0110 1100 1111 0010 Object Code 0110 0000 0000 0001 0010 0011 0100 0101 0110 0100 0000 0000 TSTFSZ MOVFF ADDWF REG1 ; REG1, REG2 ; ; REG3 ; CASE 2: 0110 1100 1111 0010 Object Code 0110 0000 0000 0001 0010 0011 0100 0101 0110 0100 0000 0000 TSTFSZ MOVFF ADDWF Source Code REG1 ; is RAM location 0? REG1, REG2 ; Yes ; 2nd operand becomes NOP REG3 ; continue code 2000 Microchip Technology Inc. Advanced Information DS30475A-page 47 PIC18CXX8 4.9 Data Memory Organization 4.9.1 GENERAL PURPOSE REGISTER FILE The data memory is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. Figure 4-4 shows the data memory organization for the PIC18CXX8 devices. The data memory map is divided into as many as 16 banks that contain 256 bytes each. The lower 4 bits of the Bank Select Register (BSR<3:0>) select which bank will be accessed. The upper 4 bits for the BSR are not implemented. The data memory contains Special Function Registers (SFR) and General Purpose Registers (GPR). The SFR's are used for control and status of the controller and peripheral functions, while GPR's are used for data storage and scratch pad operations in the user's application. The SFR's start at the last location of Bank 15 (0xFFF) and grow downwards. GPR's start at the first location of Bank 0 and grow upwards. Any read of an unimplemented location will read as '0's. The entire data memory may be accessed directly or indirectly. Direct addressing may require the use of the BSR register. Indirect addressing requires the use of the File Select Register (FSR). Each FSR holds a 12-bit address value that can be used to access any location in the Data Memory map without banking. The instruction set and architecture allow operations across all banks. This may be accomplished by indirect addressing or by the use of the MOVFF instruction. The MOVFF instruction is a two word/two cycle instruction that moves a value from one register to another. To ensure that commonly used registers (SFR's and select GPR's) can be accessed in a single cycle, regardless of the current BSR values, an Access Bank is implemented. A segment of Bank 0 and a segment of Bank 15 comprise the Access RAM. Section 4.10 provides a detailed description of the Access RAM. The register file can be accessed either directly or indirectly. Indirect addressing operates through the File Select Registers (FSR). The operation of indirect addressing is shown in Section 4.12. Enhanced MCU devices may have banked memory in the GPR area. GPR's are not initialized by a Power-on Reset and are unchanged on all other RESETS. Data RAM is available for use as GPR registers by all instructions. Bank 15 (0xF00 to 0xFFF) contains SFR's. All other banks of data memory contain GPR registers starting with bank 0. 4.9.2 SPECIAL FUNCTION REGISTERS The Special Function Registers (SFR's) are registers used by the CPU and Peripheral Modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 4-2. The SFR's can be classified into two sets: those associated with the "core" function and those related to the peripheral functions. Those registers related to the "core" are described in this section, while those related to the operation of the peripheral features are described in the section of that peripheral feature. The SFR's are typically distributed among the peripherals whose functions they control. The unused SFR locations will be unimplemented and read as '0's. See Table 4-2 for addresses for the SFR's. DS30475A-page 48 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 4-4: BSR<3:0> = 0000b 00h Bank 0 FFh 00h Bank 1 FFh 00h Bank 2 FFh 00h Bank 3 FFh = 0100b Bank 4 00h Bank 5 FFh GPR's 5FFh 600h GPR's 4FFh 500h GPR's 3FFh 400h Access Bank 00h Access Bank low 5Fh (GPR's) 60h Access Bank high FFh (SFR's) DATA MEMORY MAP FOR PIC18C658/858 Data Memory Map Access GPR's GPR's GPR's 1FFh 200h GPR's 2FFh 300h 000h 05Fh 060h 0FFh 100h = 0001b = 0010b = 0011b = 0101b = 0110b = 1110b Bank 6 to Bank 14 Unused Read '00h' When a = 0, the BSR is ignored and the Access Bank is used. The first 96 bytes are General Purpose RAM (from Bank 0). = 1111b 00h Bank 15 FFh SFR's Access SFR's EFFh F00h F5Fh F60h FFFh The next 160 bytes are Special Function Registers (from Bank 15). When a = 1, the BSR is used to specify the RAM location that the instruction uses. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 49 PIC18CXX8 TABLE 4-2: Address SPECIAL FUNCTION REGISTER MAP Name Address Name (2) (2) Address Name Address Name FFFh TOSU FFEh TOSH FFDh TOSL FFCh STKPTR FFBh PCLATU FFAh PCLATH FF9h PCL FF8h TBLPTRU FF7h TBLPTRH FF6h TBLPTRL FF5h TABLAT FF4h PRODH FF3h PRODL FF2h INTCON FF1h INTCON2 FF0h INTCON3 FEFh INDF0 (2) (2) FDFh INDF2 FBFh CCPR1H FBEh CCPR1L FBDh CCP1CON FBCh CCPR2H FBBh CCPR2L FBAh CCP2CON FB9h FB8h FB7h FB6h -- -- -- -- F9Fh IPR1 F9Eh PIR1 F9Dh PIE1 F9Ch F9Bh -- -- FDEh POSTINC2 FDDh POSTDEC2(2) FDCh PREINC2(2) FDBh PLUSW2(2) FDAh FSR2H FD9h FSR2L FD8h STATUS FD7h TMR0H FD6h TMR0L FD5h T0CON FD4h -- FD3h OSCCON FD2h LVDCON FD1h WDTCON FD0h RCON FCFh TMR1H FCEh TMR1L FCDh T1CON FCCh TMR2 FCBh PR2 FCAh T2CON FC9h SSPBUF FC8h SSPADD FC7h SSPSTAT FC6h SSPCON1 FC5h SSPCON2 FC4h ADRESH FC3h ADRESL FC2h ADCON0 FC1h ADCON1 FC0h ADCON2 F9Ah TRISJ(5) F99h TRISH(5) F98h TRISG F97h TRISF F96h TRISE F95h TRISD F94h TRISC F93h TRISB F92h TRISA F91h LATJ(5) F90h LATH(5) F8Fh LATG F8Eh LATF F8Dh LATE F8Ch LATD F8Bh LATC FB5h CVRCON FB4h CMCON FB3h TMR3H FB2h TMR3L FB1h T3CON FB0h PSPCON FAFh SPBRG FAEh RCREG FADh TXREG FACh TXSTA FABh RCSTA FAAh FA9h FA8h FA7h FA6h FA5h IPR3 FA4h PIR3 FA3h PIE3 FA2h IPR2 FA1h PIR2 FA0h PIE2 -- -- -- -- -- FEEh POSTINC0 FEDh POSTDEC0(2) FECh PREINC0(2) FEBh PLUSW0(2) FEAh FSR0H FE9h FSR0L FE8h WREG FE7h INDF1 (2) F8Ah LATB F89h LATA F88h PORTJ(5) F87h PORTH(5) F86h PORTG F85h PORTF F84h PORTE F83h PORTD F82h PORTC F81h PORTB F80h PORTA FE6h POSTINC1(2) FE5h POSTDEC1(2) FE4h PREINC1 FE2h FSR1H FE1h FSR1L FE0h BSR Note 1: 2: 3: 4: (2) FE3h PLUSW1(2) Unimplemented registers are read as '0'. This is not a physical register. Contents of register is dependent on WIN2:WIN0 bits in CANCON register. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 5: Available on PIC18C858 only. DS30475A-page 50 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Address Name Address F5Fh Name -- Address F3Fh Name -- Address Name F7Fh TRISK(5) F7Eh LATK(5) F7Dh PORTK(5) F7Ch F7Bh F7Ah F79h F78h F77h -- -- -- -- -- -- F1Fh RXM1EID0 F1Eh RXM1EID8 F1Dh RXM1SIDL F1Ch RXM1SIDH F1Bh RXM0EID0 F1Ah RXM0EID8 F19h RXM0SIDL F18h RXM0SIDH F17h RXF5EID0 F16h RXF5EID8 F15h RXF5SIDL F14h RXF5SIDH F13h RXF4EID0 F12h RXF4EID8 F11h RXF4SIDL F10h RXF4SIDH F0Fh RXF3EID0 F0Eh RXF3EID8 F0Dh RXF3SIDL F0Ch RXF3SIDH F0Bh RXF2EID0 F0Ah RXF2EID8 F09h RXF2SIDL F08h RXF2SIDH F07h RXF1EID0 F06h RXF1EID8 F05h RXF1SIDL F04h RXF1SIDH F03h RXF0EIDL F02h RXF0EIDH F01h RXF0SIDL F00h RXF0SIDH F5Eh CANSTATRO0(4) F5Dh RXB1D7 F5Ch RXB1D6 F5Bh RXB1D5 F5Ah RXB1D4 F59h RXB1D3 F58h RXB1D2 F57h RXB1D1 F56h RXB1D0 F55h RXB1DLC F54h RXB1EIDL F53h RXB1EIDH F52h RXB1SIDL F51h RXB1SIDH F50h RXB1CON F4Fh -- F4Eh CANSTATRO1(4) F4Dh TXB0D7 F4Ch TXB0D6 F4Bh TXB0D5 F4Ah TXB0D4 F49h TXB0D3 F48h TXB0D2 F47h TXB0D1 F46h TXB0D0 F45h TXB0DLC F44h TXB0EIDL F43h TXB0EIDH F42h TXB0SIDL F41h TXB0SIDH F40h TXB0CON F3Eh CANSTATRO2(4) F3Dh TXB1D7 F3Ch TXB1D6 F3Bh TXB1D5 F3Ah TXB1D4 F39h TXB1D3 F38h TXB1D2 F37h TXB1D1 F36h TXB1D0 F35h TXB1DLC F34h TXB1EIDL F33h TXB1EIDH F32h TXB1SIDL F31h TXB1SIDH F30h TXB1CON F2Fh -- F2Eh CANSTATRO3(4) F2Dh TXB2D7 F2Ch TXB2D6 F2Bh TXB2D5 F2Ah TXB2D4 F29h TXB2D3 F28h TXB2D2 F27h TXB2D1 F26h TXB2D0 F25h TXB2DLC F24h TXB2EIDL F23h TXB2EIDH F22h TXB2SIDL F21h TXB2SIDH F20h TXB2CON F76h TXERRCNT F75h RXERRCNT F74h COMSTAT F73h CIOCON F72h BRGCON3 F71h BRGCON2 F70h BRGCON1 F6Fh CANCON F6Eh CANSTAT F6Dh RXB0D7(3) F6Ch RXB0D6(3) F6Bh RXB0D5(3) F6Ah RXB0D4(3) F69h RXB0D3(3) F68h RXB0D2(3) F67h RXB0D1(3) F66h RXB0D0(3) F65h RXB0DLC(3) F64h RXB0EIDL(3) F63h RXB0EIDH(3) F62h RXB0SIDL(3) F61h RXB0SIDH(3) F60h RXB0CON(3) Note: Note 1: 2: 3: 4: Shaded registers are available in Bank 15, while the rest are in Access Bank low. Unimplemented registers are read as '0'. This is not a physical register. Contents of register is dependent on WIN2:WIN0 bits in CANCON register. CANSTAT register is repeated in these locations to simplify application firmware. Unique names are given for each instance of the CANSTAT register due to the Microchip Header file requirement. 5: Available on PIC18C858 only. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 51 PIC18CXX8 TABLE 4-3: Filename REGISTER FILE SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 Return Stack Pointer Holding Register for PC<20:16> 00-0 0000 --00 0000 0000 0000 0000 0000 bit 21(2) Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) ---0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 INT3IE INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 0000 000x 1111 1111 1100 0000 n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx xxxx xxxx n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx Bank Select Register ---- 0000 Value on all other RESETS(3) ---0 0000 0000 0000 0000 0000 00-0 0000 --00 0000 0000 0000 0000 0000 ---0 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 1111 1100 0000 n/a n/a n/a n/a n/a ---- 0000 uuuu uuuu uuuu uuuu n/a n/a n/a n/a n/a ---- 0000 uuuu uuuu ---- 0000 TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR Legend: Note 1: 2: 3: 4: -- -- -- Top-of-Stack upper Byte (TOS<20:16>) Top-of-Stack High Byte (TOS<15:8>) Top-of-Stack Low Byte (TOS<7:0>) STKFUL STKUNF -- bit 21(3) -- -- Holding Register for PC<15:8> PC Low Byte (PC<7:0>) -- -- Program Memory Table Pointer High Byte (TBLPTR<15:8>) Program Memory Table Pointer Low Byte (TBLPTR<7:0>) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP Uses contents of FSR0 to address data memory - value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory - value of FSR0 pre-incremented (not a physical register) - value of FSR0 offset by WREG -- Working Register -- -- -- Indirect Data Memory Address Pointer 0 High Indirect Data Memory Address Pointer 0 Low Byte Uses contents of FSR1 to address data memory - value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory - value of FSR1 pre-incremented (not a physical register) - value of FSR1 offset by WREG -- -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 1 High Indirect Data Memory Address Pointer 1 Low Byte x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. DS30475A-page 52 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR n/a n/a n/a n/a n/a ---- 0000 xxxx xxxx N OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS T0SE T0PS3 T0PS2 T0PS1 T0PS0 SCS LVDL0 1111 1111 ---- ---0 --00 0101 Value on all other RESETS(3) n/a n/a n/a n/a n/a ---- 0000 uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 ---- ---0 --00 0101 ---- ---0 00-q qquu uuuu uuuu uuuu uuuu u-uu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu --00 0000 -000 0000 0--- -000 INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON LVDCON WDTCON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSPBUF SSPADD SSPSTAT SSPCON1 SSPCON2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 Legend: Note 1: 2: 3: 4: Uses contents of FSR2 to address data memory - value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) Uses contents of FSR2 to address data memory - value of FSR2 pre-incremented (not a physical register) - value of FSR2 offset by WREG -- -- -- -- -- -- -- Indirect Data Memory Address Pointer 2 High Indirect Data Memory Address Pointer 2 Low Byte Timer0 register high byte Timer0 register low byte TMR0ON T08BIT -- -- -- IPEN -- -- -- LWRT -- IRVST -- LVDEN -- LVDL3 -- LVDL2 -- LVDL1 -- -- -- RI -- TO -- PD -- POR SWDTEN ---- ---0 BOR 00-1 11qq xxxx xxxx xxxx xxxx Timer1 Register High Byte Timer1 Register Low Byte RD16 Timer2 Register Timer2 Period Register -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 0000 0000 1111 1111 -- TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx SSP Receive Buffer/Transmit Register SSP Address Register in I C Slave mode. SSP Baud Rate Reload Register in I C Master mode. SMP WCOL GCEN CKE SSPOV ACKSTAT D/A SSPEN ACKDT P CKP ACKEN S SSPM3 RCEN R/W SSPM2 PEN UA SSPM1 RSEN BF SSPM0 SEN 2 2 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx A/D Result Register High Byte A/D Result Register Low Byte -- -- ADFM -- -- -- CHS3 VCFG1 CHS2 VCFG0 CHS1 PCFG3 CHS0 PCFG2 ADCS2 GO/DONE PCFG1 ADCS1 ADON PCFG0 ADCS0 --00 0000 -000 0000 0--- -000 -- -- -- x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 53 PIC18CXX8 Filename Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx DC1B0 CCPM3 CCP1M2 CCP1M1 CCP1M0 --00 0000 xxxx xxxx xxxx xxxx DC2B0 VRSS C1INV CCPM3 VR3 CIS CCP2M2 VR2 CM2 CCP2M1 VR1 CM1 CCP2M0 VR0 CM0 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx T3CKPS1 IBOV T3CKPS0 PSPMODE T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 0000 ---0000 0000 0000 0000 0000 0000 TXEN SREN ERRIP ERRIF ERRIE SYNC CREN TXB2IP TXB2IF TXB2IE Value on all other RESETS(3) uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu 0000 ---0000 0000 0000 0000 0000 0000 0000 -010 0000 000x 1111 1111 0000 0000 0000 0000 -1-- 1111 -0-- 0000 -0-- 0000 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 ---1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 CCPR1H CCPR1L CCP1CON CCPR2H CCPR2L CCP2CON VRCON CMCON TMR3H TMR3L T3CON PSPCON SPBRG RCREG TXREG TXSTA RCSTA IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 TRISJ(4) TRISH(4) TRISG TRISF TRISE TRISD TRISC TRISB TRISA Legend: Note 1: 2: 3: 4: Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte -- -- DC1B1 Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte -- VREN C2OUT -- VROEN C1OUT DC2B1 VRR C2INV Timer3 Register High Byte Timer3 Register Low Byte RD16 IBF T3CCP2 OBF -- -- -- -- USART Baud Rate Generator USART Receive Register USART Transmit Register CSRC SPEN IRXIP IRXIF IRXIE TX9 RX9 WAKIP WAKIF WAKIE CMIP CMIF CMIE ADIP ADIF ADIE -- ADEN TXB1IP TXB1IF TXB1IE BCLIP BCLIF BCLIE SSPIP SSPIF SSPIE BRGH FERR TXB0IP TXB0IF TXB0IE LVDIP LVDIF LVDIE CCP1IP CCP1IF CCP1IE TRMT OERR RXB1IP RXB1IF RXB1IE TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE TX9D RX9D RXB0IP RXB0IF RXB0IE CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE 0000 -010 0000 000x 1111 1111 0000 0000 0000 0000 -1-- 1111 -0-- 0000 -0-- 0000 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 -- -- -- PSPIP PSPIF PSPIE -- -- -- RCIP RCIF RCIE -- -- -- TXIP TXIF TXIE Data Direction Control Register for PORTJ Data Direction Control Register for PORTH -- -- -- Data Direction Control Register for PORTG ---1 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 --11 1111 Data Direction Control Register for PORTF Data Direction Control Register for PORTE Data Direction Control Register for PORTD Data Direction Control Register for PORTC Data Direction Control Register for PORTB -- Bit 6 (1) Data Direction Control Register for PORTA x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. DS30475A-page 54 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Filename LATJ(4) LATH(4) LATG LATF LATE LATD LATC LATB LATA PORTJ(4) PORTH(4) PORTG PORTF PORTE PORTD PORTC PORTB PORTA TRISK (4) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx ---x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --xx xxxx xxxx xxxx xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx --0x 0000 1111 1111 xxxx xxxx xxxx xxxx Value on all other RESETS(3) uuuu uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --0u 0000 1111 1111 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 0000 0000 1000 ----0-- -000 0000 0000 0000 0000 uuuu uuuuuu- uuu- Read PORTJ Data Latch, Write PORTJ Data Latch Read PORTH Data Latch, Write PORTH Data Latch -- -- -- Read PORTG Data Latch, Write PORTG Data Latch Read PORTF Data Latch, Write PORTF Data Latch Read PORTE Data Latch, Write PORTE Data Latch Read PORTD Data Latch, Write PORTD Data Latch Read PORTC Data Latch, Write PORTC Data Latch Read PORTB Data Latch, Write PORTB Data Latch -- Bit 6(1) Read PORTA Data Latch, Write PORTA Data Latch Read PORTJ pins, Write PORTJ Data Latch Read PORTH pins, Write PORTH Data Latch -- -- -- Read PORTG pins, Write PORTG Data Latch Read PORTF pins, Write PORTF Data Latch Read PORTE pins, Write PORTE Data Latch Read PORTD pins, Write PORTD Data Latch Read PORTC pins, Write PORTC Data Latch Read PORTB pins, Write PORTB Data Latch -- Bit 6(1) Read PORTA pins, Write PORTA Data Latch Data Direction Control Register for PORTK Read PORTK Data Latch, Write PORTK Data Latch LATK(4) PORTK (4) Read PORTK pins, Write PORTK Data Latch TEC7 REC7 RXB0OVFL TX1SRC TEC6 REC6 RXB1OVFL TX1EN WAKFIL SAM SJW0 REQOP1 OPMODE1 TEC5 REC5 TXBO ENDRHI TEC4 REC4 TXBP CANCAP TEC3 REC3 RXBP TEC2 REC2 TXWARN TEC1 REC1 RXWARN TEC0 REC0 EWARN TXERRCNT RXERRCNT COMSTAT CIOCON BRGCON3 BRGCON2 BRGCON1 CANCON CANSTAT Legend: Note 1: 2: 3: 4: 0000 0000 0000 0000 0000 0000 1000 ----0-- -000 0000 0000 0000 0000 xxxx xxxxxx- xxx- -- -- SEG1PH0 BRP3 WIN2 ICODE2 -- SEG2PH2 PRSEG2 BRP2 WIN1 ICODE1 -- SEG2PH1 PRSEG1 BRP1 WIN0 ICOED0 -- SEG2PH0 PRSEG0 BRP0 -- SEG2PHTS SJW1 REQOP2 OPMODE2 -- SEG1PH2 BRP5 REQOP0 OPMODE0 -- SEG1PH1 BRP4 ABAT -- -- -- x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 55 PIC18CXX8 Filename Bit 7 RXB0D77 RXB0D67 RXB0D57 RXB0D47 RXB0D37 RXB0D27 RXB0D17 RXB0D07 Bit 6 RXB0D76 RXB0D66 RXB0D56 RXB0D46 RXB0D36 RXB0D26 RXB0D16 RXB0D06 RXRTR EID6 EID14 SID1 SID9 RXM1 OPMODE1 RXB1D76 RXB1D66 RXB1D56 RXB1D46 RXB1D36 RXB1D26 RXB1D16 RXB1D06 RXRTR EID6 EID14 SID1 SID9 RXM1 OPMODE1 Bit 5 RXB0D75 RXB0D65 RXB0D55 RXB0D45 RXB0D35 RXB0D25 RXB0D15 RXB0D05 RESB1 EID5 EID13 SID0 SID8 RXM0 OPMODE0 RXB1D75 RXB1D65 RXB1D55 RXB1D45 RXB1D35 RXB1D25 RXB1D15 RXB1D05 RESB1 EID5 EID13 SID0 SID8 RXM0 OPMODE0 Bit 4 RXB0D74 RXB0D64 RXB0D54 RXB0D44 RXB0D34 RXB0D24 RXB0D14 RXB0D04 RESB0 EID4 EID12 SRR SID7 Bit 3 RXB0D73 RXB0D63 RXB0D53 RXB0D43 RXB0D33 RXB0D23 RXB0D13 RXB0D03 DLC3 EID3 EID11 EXID SID6 Bit 2 RXB0D72 RXB0D62 RXB0D52 RXB0D42 RXB0D32 RXB0D22 RXB0D12 RXB0D02 DLC2 EID2 EID10 Bit 1 RXB0D71 RXB0D61 RXB0D51 RXB0D41 RXB0D31 RXB0D21 RXB0D11 RXB0D0? DLC1 EID1 EID9 EID17 SID4 JTOFF ICODE0 RXB1D71 RXB1D61 RXB1D51 RXB1D41 RXB1D31 RXB1D21 RXB1D11 RXB1D01 DLC1 EID1 EID9 EID17 SID4 FILHIT1 ICODE0 Bit 0 RXB0D70 RXB0D60 RXB0D50 RXB0D40 RXB0D30 RXB0D20 RXB0D10 RXB0D00 DLC0 EID0 EID8 EID16 SID3 FILHIT0 Value on POR, BOR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0xxx xxxx xxxx xxxx xxxx xxxx xxxx x-xx xxxx xxxx 000- 0000 xxx- xxxxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0xxx xxxx xxxx xxxx xxxx xxxx xxxx x0xx xxxx xxxx 0000 0000 xxx- xxxValue on all other RESETS(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu 000- 0000 uuu- uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0uuu uuuu uuuu uuuu uuuu uuuu uuuu u0uu uuuu uuuu 0000 0000 uuu- uuu- RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON CANSTAT RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON CANSTAT Legend: Note 1: 2: 3: 4: -- EID7 EID15 SID2 SID10 RXFUL OPMODE2 RXB1D77 RXB1D67 RXB1D57 RXB1D47 RXB1D37 RXB1D27 RXB1D17 RXB1D07 -- SID5 -- -- RXB1D74 RXB1D64 RXB1D54 RXB1D44 RXB1D34 RXB1D24 RXB1D14 RXB1D04 RESB0 EID4 EID12 SRR SID7 RXRTRRO RXB0DBEN ICODE2 RXB1D73 RXB1D63 RXB1D53 RXB1D43 RXB1D33 RXB1D23 RXB1D13 RXB1D03 DLC3 EID3 EID11 EXID SID6 RXRTRRO ICODE2 ICODE1 RXB1D72 RXB1D62 RXB1D52 RXB1D42 RXB1D32 RXB1D22 RXB1D12 RXB1D02 DLC2 EID2 EID10 -- RXB1D70 RXB1D60 RXB1D50 RXB1D40 RXB1D30 RXB1D20 RXB1D10 RXB1D00 DLC0 EID0 EID8 EID16 SID3 FILHIT0 -- EID7 EID15 SID2 SID10 RXFUL OPMODE2 -- SID5 FILHIT2 ICODE1 -- -- -- x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. DS30475A-page 56 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Filename Bit 7 TXB0D77 TXB0D67 TXB0D57 TXB0D47 TXB0D37 TXB0D27 TXB0D17 TXB0D07 Bit 6 TXB0D76 TXB0D66 TXB0D56 TXB0D46 TXB0D36 TXB0D26 TXB0D16 TXB0D06 TXRTR EID6 EID14 SID1 SID9 TXABT OPMODE1 TXB1D76 TXB1D66 TXB1D56 TXB1D46 TXB1D36 TXB1D26 TXB1D16 TXB1D06 TXRTR EID6 EID14 SID1 SID9 TXABT OPMODE1 Bit 5 TXB0D75 TXB0D65 TXB0D55 TXB0D45 TXB0D35 TXB0D25 TXB0D15 TXB0D05 Bit 4 TXB0D74 TXB0D64 TXB0D54 TXB0D44 TXB0D34 TXB0D24 TXB0D14 TXB0D04 Bit 3 TXB0D73 TXB0D63 TXB0D53 TXB0D43 TXB0D33 TXB0D23 TXB0D13 TXB0D03 DLC3 EID3 EID11 EXIDEN SID6 TXREQ ICODE2 TXB1D73 TXB1D63 TXB1D53 TXB1D43 TXB1D33 TXB1D23 TXB1D13 TXB1D03 DLC3 EID3 EID11 EXIDE SID6 TXREQ ICODE2 Bit 2 TXB0D72 TXB0D62 TXB0D52 TXB0D42 TXB0D32 TXB0D22 TXB0D12 TXB0D02 DLC2 EID2 EID10 Bit 1 TXB0D71 TXB0D61 TXB0D51 TXB0D41 TXB0D31 TXB0D21 TXB0D11 TXB0D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 ICODE0 TXB1D71 TXB1D61 TXB1D51 TXB1D41 TXB1D31 TXB1D21 TXB1D11 TXB1D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 ICODE0 Bit 0 TXB0D70 TXB0D60 TXB0D50 TXB0D40 TXB0D30 TXB0D20 TXB0D10 TXB0D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 Value on POR, BOR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0x00 xxxx xxxx xxxx xxxx xxxx xxx0 x0xx xxxx xxxx 0000 0000 xxx- xxxxxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0x00 xxxx xxxx xxxx xxxx xxxx xxx0 x0xx xxxx xxxx 0000 0000 xxx- xxxValue on all other RESETS(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0u00 uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu 0000 0000 uuu- uuuuuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0u00 uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu 0000 0000 uuu- uuu- TXB0D7 TXB0D6 TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON CANSTAT TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON CANSTAT Legend: Note 1: 2: 3: 4: -- EID7 EID15 SID2 SID10 -- EID5 EID13 SID0 SID8 TXLARB OPMODE0 TXB1D75 TXB1D65 TXB1D55 TXB1D45 TXB1D35 TXB1D25 TXB1D15 TXB1D05 -- EID4 EID12 -- SID7 TXERR -- SID5 -- OPMODE2 TXB1D77 TXB1D67 TXB1D57 TXB1D47 TXB1D37 TXB1D27 TXB1D17 TXB1D07 -- ICODE1 TXB1D72 TXB1D62 TXB1D52 TXB1D42 TXB1D32 TXB1D22 TXB1D12 TXB1D02 DLC2 EID2 EID10 -- TXB1D74 TXB1D64 TXB1D54 TXB1D44 TXB1D34 TXB1D24 TXB1D14 TXB1D04 -- TXB1D70 TXB1D60 TXB1D50 TXB1D40 TXB1D30 TXB1D20 TXB1D10 TXB1D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 -- EID7 EID15 SID2 SID10 -- EID5 EID13 SID0 SID8 TXLARB OPMODE0 -- EID4 EID12 -- SID7 TXERR -- SID5 -- OPMODE2 -- ICODE1 -- -- x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 57 PIC18CXX8 Filename Bit 7 TXB2D77 TXB2D67 TXB2D57 TXB2D47 TXB2D37 TXB2D27 TXB2D17 TXB2D07 Bit 6 TXB2D76 TXB2D66 TXB2D56 TXB2D46 TXB2D36 TXB2D26 TXB2D16 TXB2D06 TXRTR EID6 EID14 SID1 SID9 TXABT EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 Bit 5 TXB2D75 TXB2D65 TXB2D55 TXB2D45 TXB2D35 TXB2D25 TXB2D15 TXB2D05 Bit 4 TXB2D74 TXB2D64 TXB2D54 TXB2D44 TXB2D34 TXB2D24 TXB2D14 TXB2D04 Bit 3 TXB2D73 TXB2D63 TXB2D53 TXB2D43 TXB2D33 TXB2D23 TXB2D13 TXB2D03 DLC3 EID3 EID11 EXIDEN SID6 TXREQ EID3 EID11 Bit 2 TXB2D72 TXB2D62 TXB2D52 TXB2D42 TXB2D32 TXB2D22 TXB2D12 TXB2D02 DLC2 EID2 EID10 Bit 1 TXB2D71 TXB2D61 TXB2D51 TXB2D41 TXB2D31 TXB2D21 TXB2D11 TXB2D01 DLC1 EID1 EID9 EID17 SID4 TXPRI1 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 Bit 0 TXB2D70 TXB2D60 TXB2D50 TXB2D40 TXB2D30 TXB2D20 TXB2D10 TXB2D00 DLC0 EID0 EID8 EID16 SID3 TXPRI0 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 Value on POR, BOR xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0x00 xxxx xxxx xxxx xxxx xxxx xxx0 x0xx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- --xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx Value on all other RESETS(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0u00 uuuu uuuu uuuu uuuu uuuu uuu0 u0uu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- --uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu TXB2D7 TXB2D6 TXB2D5 TXB2D4 TXB2D3 TXB2D2 TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EID0 RXF5EID8 RXF5SIDL RXF5SIDH RXF4EID0 RXF4EID8 RXF4SIDL RXF4SIDH RXF3EID0 RXF3EID8 RXF3SIDL RXF3SIDH Legend: Note 1: 2: 3: 4: -- EID7 EID15 SID2 SID10 -- EID5 EID13 SID0 SID8 TXLARB EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 -- EID4 EID12 -- SID7 TXERR EID4 EID12 -- SID5 -- EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 -- EID2 EID10 -- SID7 EID4 EID12 -- SID6 EID3 EID11 -- SID5 EID2 EID10 -- SID7 EID4 EID12 -- SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 -- SID5 EID2 EID10 -- SID7 EID4 EID12 -- SID5 EID2 EID10 -- SID7 EID4 EID12 -- SID5 EID2 EID10 -- SID7 -- SID5 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. DS30475A-page 58 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Filename Bit 7 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 EID7 EID15 SID2 SID10 Bit 6 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 EID6 EID14 SID1 SID9 Bit 5 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 EID5 EID13 SID0 SID8 Bit 4 EID4 EID12 Bit 3 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 EID3 EID11 EXIDEN SID6 Bit 2 EID2 EID10 Bit 1 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 EID1 EID9 EID17 SID4 Bit 0 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 EID0 EID8 EID16 SID3 Value on POR, BOR xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx xxxx xxxx xxxx xxxx xxx- x-xx xxxx xxxx Value on all other RESETS(3) uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuu- u-uu uuuu uuuu RXF2EID0 RXF2EID8 RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDL RXF0EIDH RXF0SIDL RXF0SIDH Legend: Note 1: 2: 3: 4: -- SID7 EID4 EID12 -- SID5 EID2 EID10 -- SID7 EID4 EID12 -- SID5 EID2 EID10 -- SID7 -- SID5 x = unknown, u = unchanged, - = unimplemented, q = value depends on condition Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. Bit 21 of the TBLPTRU allows access to the device configuration bits. Other (non-power-up) RESETs include external RESET through MCLR and Watchdog Timer Reset. These registers are reserved on PIC18C658. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 59 PIC18CXX8 4.10 Access Bank 4.11 Bank Select Register (BSR) The Access Bank is an architectural enhancement that is very useful for C compiler code optimization. The techniques used by the C compiler are also be useful for programs written in assembly. This data memory region can be used for: * * * * * Intermediate computational values Local variables of subroutines Faster context saving/switching of variables Common variables Faster evaluation/control of SFR's (no banking) The need for a large general purpose memory space dictates a RAM banking scheme. The data memory is partitioned into sixteen banks. When using direct addressing, the BSR should be configured for the desired bank. BSR<3:0> holds the upper 4 bits of the 12-bit RAM address. The BSR<7:4> bits will always read '0's, and writes will have no effect. A MOVLB instruction has been provided in the instruction set to assist in selecting banks. If the currently selected bank is not implemented, any read will return all '0's and all writes are ignored. The STATUS register bits will be set/cleared as appropriate for the instruction performed. Each Bank extends up to FFh (256 bytes). All data memory is implemented as static RAM. A MOVFF instruction ignores the BSR, since the 12-bit addresses are embedded into the instruction word. Section 4.12 provides a description of indirect addressing, which allows linear addressing of the entire RAM space. The Access Bank is comprised of the upper 160 bytes in Bank 15 (SFR's) and the lower 96 bytes in Bank 0. These two sections will be referred to as Access Bank High and Access Bank Low, respectively. Figure 4-4 indicates the Access Bank areas. A bit in the instruction word specifies if the operation is to occur in the bank specified by the BSR register, or in the Access Bank. When forced in the Access Bank (a = '0'), the last address in Access Bank Low is followed by the first address in Access Bank High. Access Bank High maps most of the Special Function Registers so that these registers can be accessed without any software overhead. FIGURE 4-5: DIRECT ADDRESSING Direct Addressing BSR<3:0> 7 from opcode(3) 0 bank select(2) location select(3) 00h 000h 01h 100h 0Eh E00h 0Fh F00h Data Memory(1) 0FFh 1FFh EFFh FFFh Bank 0 Note 1: For register file map detail, see Table 4-2. Bank 1 Bank 14 Bank 15 2: The access bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank. 3: The MOVFF instruction embeds the entire 12-bit address in the instruction. DS30475A-page 60 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 4.12 Indirect Addressing, INDF and FSR Registers If an instruction writes a value to INDF0, the value will be written to the address indicated by FSR0H:FSR0L. A read from INDF1 reads the data from the address indicated by FSR1H:FSR1L. INDFn can be used in code anywhere an operand can be used. If INDF0, INDF1 or INDF2 are read indirectly via an FSR, all '0's are read (zero bit is set). Similarly, if INDF0, INDF1 or INDF2 are written to indirectly, the operation will be equivalent to a NOP instruction and the STATUS bits are not affected. 4.12.1 INDIRECT ADDRESSING OPERATION Indirect addressing is a mode of addressing data memory, where the data memory address in the instruction is not fixed. A SFR register is used as a pointer to the data memory location that is to be read or written. Since this pointer is in RAM, the contents can be modified by the program. This can be useful for data tables in the data memory and for software stacks. Figure 4-6 shows the operation of indirect addressing. This shows the moving of the value to the data memory address specified by the value of the FSR register. Indirect addressing is possible by using one of the INDF registers. Any instruction using the INDF register actually accesses the register indicated by the File Select Register, FSR. Reading the INDF register itself indirectly (FSR = '0') will read 00h. Writing to the INDF register indirectly results in a no-operation. The FSR register contains a 12-bit address, which is shown in Figure 4-6. The INDFn (0 n 2) register is not a physical register. Addressing INDFn actually addresses the register whose address is contained in the FSRn register (FSRn is a pointer). This is indirect addressing. Example 4-4 shows a simple use of indirect addressing to clear the RAM in Bank 1 (locations 100h-1FFh) in a minimum number of instructions. Each FSR register has an INDF register associated with it, plus four additional register addresses. Performing an operation on one of these five registers determines how the FSR will be modified during indirect addressing. When data access is done to one of the five INDFn locations, the address selected will configure the FSRn register to: * Do nothing to FSRn after an indirect access (no change) - INDFn * Auto-decrement FSRn after an indirect access (post-decrement) - POSTDECn * Auto-increment FSRn after an indirect access (post-increment) - POSTINCn * Auto-increment FSRn before an indirect access (pre-increment) - PREINCn * Use the value in the WREG register as an offset to FSRn. Do not modify the value of the WREG or the FSRn register after an indirect access (no change) - PLUSWn When using the auto-increment or auto-decrement features, the effect on the FSR is not reflected in the STATUS register. For example, if the indirect address causes the FSR to equal '0', the Z bit will not be set. Incrementing or decrementing an FSR affects all 12 bits. That is, when FSRnL overflows from an increment, FSRnH will be incremented automatically. Adding these features allows the FSRn to be used as a software stack pointer in addition to its uses for table operations in data memory. Each FSR has an address associated with it that performs an indexed indirect access. When a data access to this INDFn location (PLUSWn) occurs, the FSRn is configured to add the 2's complement value in the WREG register and the value in FSR to form the address before an indirect access. The FSR value is not changed. If an FSR register contains a value that indicates one of the INDFn, an indirect read will read 00h (zero bit is set), while an indirect write will be equivalent to a NOP (STATUS bits are not affected). If an indirect addressing operation is done where the target address is an FSRnH or FSRnL register, the write operation will dominate over the pre- or post-increment/decrement functions. EXAMPLE 4-4: HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 0x100 ; POSTINC0 ; Clear INDF ; register ; & inc pointer FSR0H, 1 ; All done ; w/ Bank1? NEXT ; NO, clear next ; ; YES, continue LFSR NEXT CLRF BTFSS GOTO CONTINUE : There are three indirect addressing registers. To address the entire data memory space (4096 bytes), these registers are 12-bit wide. To store the 12-bits of addressing information, two 8-bit registers are required. These indirect addressing registers are: 1. 2. 3. FSR0: composed of FSR0H:FSR0L FSR1: composed of FSR1H:FSR1L FSR2: composed of FSR2H:FSR2L In addition, there are registers INDF0, INDF1 and INDF2, which are not physically implemented. Reading or writing to these registers activates indirect addressing, with the value in the corresponding FSR register being the address of the data. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 61 PIC18CXX8 FIGURE 4-6: INDIRECT ADDRESSING Indirect Addressing 11 8 FSRnH location select FSR register 7 FSRnL 0 0000h Data Memory(1) 0FFFh Note 1: For register file map detail, see Table 4-2. DS30475A-page 62 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 4.13 STATUS Register The STATUS register, shown in Register 4-2, contains the arithmetic status of the ALU. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will clear the upper three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register, because these instructions do not affect the Z, C, DC, OV or N bits from the STATUS register. For other instructions which do not affect the status bits, see Table 23-2. Note: The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. REGISTER 4-2: STATUS REGISTER U-0 -- bit 7 U-0 -- U-0 -- R/W-x N R/W-x OV R/W-x Z R/W-x DC R/W-x C bit 0 bit 7-5 bit 4 Unimplemented: Read as '0' N: Negative bit This bit is used for signed arithmetic (2's complement). It indicates whether the result of the ALU operation was negative, (ALU MSb = 1) 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2's complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRCF, RRNCF, RLCF, and RLNCF) instructions, this bit is loaded with either the bit 4 or bit 3 of the source register. bit 3 bit 2 bit 1 bit 0 C: Carry/borrow bit For ADDWF, ADDLW, SUBLW, and SUBWF instructions 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow, the polarity is reversed. A subtraction is executed by adding the two's complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 63 PIC18CXX8 4.13.1 RCON REGISTER Note 1: If the BOREN configuration bit is set, BOR is '1' on Power-on Reset. If the BOREN configuration bit is clear, BOR is unknown on Power-on Reset. The BOR status bit is a "don't care" and is not necessarily predictable if the brown-out circuit is disabled (the BOREN configuration bit is clear). BOR must then be set by the user and checked on subsequent RESETs to see if it is clear, indicating a brown-out has occurred. 2: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. The Reset Control (RCON) register contains flag bits that allow differentiation between the sources of a device RESET. These flags include the TO, PD, POR, BOR and RI bits. This register is readable and writable. REGISTER 4-3: RCON REGISTER R/W-0 IPEN bit 7 R/W-0 LWRT U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-0 POR R/W-0 BOR bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) LWRT: Long Write Enable bit 1 = Enable TBLWT to internal program memory Once this bit is set, it can only be cleared by a POR or MCLR Reset 0 = Disable TBLWT to internal program memory; TBLWT only to external program memory Unimplemented: Read as '0' RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed 0 = The RESET instruction was executed causing a device RESET (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down Detection Flag bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 64 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 5.0 TABLE READS/TABLE WRITES (R) All PICmicro devices have two memory spaces: the program memory space and the data memory space. Table Reads and Table Writes have been provided to move data between these two memory spaces through an 8-bit register (TABLAT). The operations that allow the processor to move data between the data and program memory spaces are: * Table Read (TBLRD) * Table Write (TBLWT) Table Read operations retrieve data from program memory and place it into the data memory space. Figure 5-1 shows the operation of a Table Read with program and data memory. Table Write operations store data from the data memory space into program memory. Figure 5-2 shows the operation of a Table Write with program and data memory. Table operations work with byte entities. A table block containing data is not required to be word aligned, so a table block can start and end at any byte address. If a table write is being used to write an executable program to program memory, program instructions will need to be word aligned. FIGURE 5-1: TABLE READ OPERATION TABLE POINTER (1) TABLE LATCH (8-bit) TABLAT TBLPTRU TBLPTRH TBLPTRL PROGRAM MEMORY Instruction: TBLRD* Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. FIGURE 5-2: TABLE WRITE OPERATION TABLE POINTER (1) TABLE LATCH (8-bit) TABLAT TBLPTRU TBLPTRH TBLPTRL PROGRAM MEMORY Instruction: TBLWT* Program Memory (TBLPTR) Note 1: Table Pointer points to a byte in program memory. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 65 PIC18CXX8 5.1 Control Registers 5.1.1 RCON REGISTER Several control registers are used in conjunction with the TBLRD and TBLWT instructions. These include: * RCON register * TABLAT register * TBLPTR registers The LWRT bit specifies the operation of Table Writes to internal memory when the VPP voltage is applied to the MCLR pin. When the LWRT bit is set, the controller continues to execute user code, but long table writes are allowed (for programming internal program memory) from user mode. The LWRT bit can be cleared only by performing either a POR or MCLR Reset. REGISTER 5-1: RCON REGISTER (ADDRESS: 0xFD0h) R/W-0 IPEN bit 7 bit 7 IPEN: Interrupt Priority Enable 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) LWRT: Long Write Enable 1 = Enable TBLWT to internal program memory 0 = Disable TBLWT to internal program memory. Note 1: Only cleared on a POR or MCLR reset. This bit has no effect on TBLWTs to external program memory. bit 5 bit 4 Unimplemented: Read as '0' RI: RESET Instruction Flag bit 1 = No RESET instruction occurred 0 = A RESET instruction occurred TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = No Brown-out Reset nor POR Reset occurred 0 = A Brown-out Reset or POR Reset occurred (must be set in software after a Brown-out Reset occurs) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 LWRT U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-0 POR R/W-0 BOR bit 0 bit 6 bit 3 bit 2 bit 1 bit 0 DS30475A-page 66 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 5.1.2 TABLAT - TABLE LATCH REGISTER The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch is used to hold 8-bit data during data transfers between program memory and data memory. 5.1.3 TBLPTR - TABLE POINTER REGISTER address up to 2 Mbytes of program memory space. The 22nd bit allows read only access to the Device ID, the User ID and the Configuration bits. The table pointer TBLPTR is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. These operations are shown in Table 5-1. These operations on the TBLPTR only affect the low order 21-bits. The Table Pointer (TBLPTR) addresses a byte within the program memory. The TBLPTR is comprised of three SFR registers (Table Pointer Upper byte, High byte and Low byte). These three registers (TBLPTRU:TBLPTRH:TBLPTRL) join to form a 22-bit wide pointer. The low order 21-bits allow the device to TABLE 5-1: Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write 2000 Microchip Technology Inc. Advanced Information DS30475A-page 67 PIC18CXX8 5.2 5.2.1 Program Memory Read/Writes TABLE READ OVERVIEW (TBLRD) The TBLRD instructions are used to read data from program memory to data memory. TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next Table Read operation. Table Reads from program memory are performed one byte at a time. The instruction will load TABLAT with the one byte from program memory pointed to by TBLPTR. 5.2.2 PROGRAM MEMORY WRITE BLOCK SIZE When a Table Write occurs to an even program memory address (TBLPTR<0> = 0), the contents of TABLAT are transferred to an internal holding register. This is performed as a short write and the program memory block is not actually programmed at this time. The holding register is not accessible by the user. When a Table Write occurs to an odd program memory address (TBLPTR<0> = 1), a long write is started. During the long write, the contents of TABLAT are written to the high byte of the program memory block and the contents of the holding register are transferred to the low byte of the program memory block. Figure 5-3 shows the holding register and the program memory write blocks. If a single byte is to be programmed, the low (even) byte of the destination program word should be read using TBLRD*, modified or changed, if required, and written back to the same address using TBLWT*+. The high (odd) byte should be read using TBLRD*, modified or changed if required, and written back to the same address using TBLWT. The write to an odd address will cause a long write to begin. This process ensures that existing data in either byte will not be changed unless desired. The program memory of PIC18CXX8 devices is written in blocks. For PIC18CXX8 devices, the write block size is 2 bytes. Consequently, Table Write operations to program memory are performed in pairs, one byte at a time. FIGURE 5-3: HOLDING REGISTER AND THE WRITE Holding Register Instruction Execution ; TABLPTR points to address n MOVLW DataLow MSB LSB DataLow MOVWF TABLAT TBLWT*+ MOVLW DataHigh ; Load low data ; byte to TABLAT ; Write it to LSB ; of Holding register ; Load high data ; byte to TABLAT ; Write it to MSB ; of Holding ; register and ; begin long ; write Program Memory n-1 n n+1 n+2 DataLow DataHigh MSB DataHigh LSB DataLow MOVWF TABLAT TBLWT* EXAMPLE 5-1: TABLE READ CODE EXAMPLE ; Read a byte from location 0x0020 CLRF TBLPTRU ; Load upper 5 bits of ; 0x0020 CLRF TBLPTRH ; Load higher 8 bits of ; 0x0020 MOVLW 0x20 ; Load 0x20 into MOVWF TBLPTRL ; TBLPTRL MOVWF TBLRD* ; Data is in TABLAT DS30475A-page 68 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 5.2.2.1 Long Write Operation 5.2.2.2 Sequence of Events The long write is what actually programs words of data into the internal memory. When a TBLWT to the MSB of the write block occurs, instruction execution is halted. During this time, programming voltage and the data stored in internal latches is applied to program memory. For a long write to occur: 1. 2. 3. MCLR/VPP pin must be at the programming voltage LWRT bit must be set TBLWT to the address of the MSB of the write block The sequence of events for programming an internal program memory location should be: 1. 2. 3. Enable the interrupt that terminates the long write. Disable all other interrupts. Clear the source interrupt flag. If Interrupt Service Routine execution is desired when the device wakes, enable global interrupts. Set LWRT bit in the RCON register. Raise MCLR/VPP pin to the programming voltage, VPP. Clear the WDT (if enabled). Set the interrupt source to interrupt at the required time. Execute the Table Write for the lower (even) byte. This will be a short write. Execute the Table Write for the upper (odd) byte. This will be a long write. The controller will HALT while programming. The interrupt wakes the controller. If GIE was set, service the interrupt request. Go to 7 if more bytes to be programmed. Lower MCLR/VPP pin to VDD. Verify the memory location (table read). Reset the device. 4. 5. 6. 7. 8. 9. If the LWRT bit is clear, a short write will occur and program memory will not be changed. If the TBLWT is not to the MSB of the write block, then the programming phase is not initiated. Setting the LWRT bit enables long writes when the MCLR pin is taken to VPP voltage. Once the LWRT bit is set, it can be cleared only by performing a POR or MCLR Reset. To ensure that the memory location has been well programmed, a minimum programming time is required. The long write can be terminated after the programming time has expired by a RESET or an interrupt. Having only one interrupt source enabled to terminate the long write, ensures that no unintended interrupts will prematurely terminate the long write. 10. 11. 12. 13. 14. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 69 PIC18CXX8 5.2.3 LONG WRITE INTERRUPTS 5.3 The long write must be terminated by a RESET or any interrupt. The interrupt source must have its interrupt enable bit set. When the source sets its interrupt flag, programming will terminate. This will occur regardless of the settings of interrupt priority bits, the GIE/GIEH bit or the PIE/GIEL bit. Depending on the states of interrupt priority bits, the GIE/GIEH bit or the PIE/GIEL bit, program execution can either be vectored to the high or low priority Interrupt Service Routine (ISR), or continue execution from where programming commenced. In either case, the interrupt flag will not be cleared when programming is terminated and will need to be cleared by the software. Unexpected Termination of Write Operations If a write is terminated by an unplanned event such as loss of power, an unexpected RESET, or an interrupt that was not disabled, the memory location just programmed should be verified and reprogrammed if needed. TABLE 5-2: GIE/ GIEH X X 0 (default) 0 (default) 1 0 (default) 1 SLEEP MODE, INTERRUPT ENABLE BITS AND INTERRUPT RESULTS PIE/ GIEL X X 0 (default) 1 Priority X X X 1 high priority (default) 0 low 0 low 1 high priority (default) Interrupt Enable 0 (default) 1 1 1 Interrupt Flag X 0 1 1 Action Long write continues even if interrupt flag becomes set during SLEEP. Long write continues, will wake when the interrupt flag is set. Terminates long write, executes next instruction. Interrupt flag not cleared. Terminates long write, executes next instruction. Interrupt flag not cleared. Terminates long write, executes next instruction. Interrupt flag not cleared. Terminates long write, branches to low priority interrupt vector. Interrupt flag can be cleared by ISR. Terminates long write, branches to high priority interrupt vector. Interrupt flag can be cleared by ISR. 0 (default) 1 1 1 1 1 0 (default) 1 1 DS30475A-page 70 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 6.0 8 X 8 HARDWARE MULTIPLIER An 8 x 8 hardware multiplier is included in the ALU of the PIC18CXX8 devices. By making the multiply a hardware operation, it completes in a single instruction cycle. This is an unsigned multiply that gives a 16-bit result. The result is stored into the 16-bit product register pair (PRODH:PRODL). The multiplier does not affect any flags in the STATUS register. Making the 8 x 8 multiplier execute in a single cycle gives the following advantages: * Higher computational throughput * Reduces code size requirements for multiply algorithms The performance increase allows the device to be used in applications previously reserved for Digital Signal Processors. Table 6-1 shows a performance comparison between enhanced devices using the single cycle hardware multiply, and performing the same function without the hardware multiply. TABLE 6-1: Routine 8 x 8 unsigned PERFORMANCE COMPARISON Multiply Method Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 24 52 36 Cycles (Max) 69 1 91 6 242 24 254 36 Time @ 40 MHz 6.9 s 100 ns 9.1 s 600 ns 24.2 s 2.4 s 25.4 s 3.6 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 9.6 s 102.6 s 14.4 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 24 s 254 s 36 s 8 x 8 signed Without hardware multiply Hardware multiply 16 x 16 unsigned Without hardware multiply Hardware multiply 16 x 16 signed Without hardware multiply Hardware multiply 2000 Microchip Technology Inc. Advanced Information DS30475A-page 71 PIC18CXX8 6.1 Operation Example 6-1 shows the sequence to perform an 8 x 8 unsigned multiply. Only one instruction is required when one argument of the multiply is already loaded in the WREG register. Example 6-2 shows the sequence to do an 8 x 8 signed multiply. To account for the sign bits of the arguments, each argument's most significant bit (MSb) is tested and the appropriate subtractions are done. Example 6-3 shows the sequence to perform a 16 x 16 unsigned multiply. Equation 6-1 shows the algorithm that is used. The 32-bit result is stored in 4 registers RES3:RES0. EQUATION 6-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L * ARG2H:ARG2L (ARG1H * ARG2H * 216) + + (ARG1H * ARG2L * 28) + (ARG1L * ARG2H * 28) (ARG1L * ARG2L) RES3:RES0 = = EXAMPLE 6-1: MOVFF MULWF 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL ARG1, WREG ARG2 EXAMPLE 6-3: MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC 16 x 16 UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; EXAMPLE 6-2: MOVFF MULWF BTFSC SUBWF MOVFF BTFSC SUBWF 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ARG1L, WREG ARG2L PRODH, RES1 PRODL, RES0 ARG1H, WREG ARG2H PRODH, RES3 PRODL, RES2 ARG1L, WREG ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, WREG ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1, WREG ARG2 ARG2, SB PRODH, F ARG2, WREG ARG1, SB PRODH, F ; Test Sign Bit ; PRODH = PRODH ; - ARG2 ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; DS30475A-page 72 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 Example 6-4 shows the sequence to perform an 16 x 16 signed multiply. Equation 6-2 shows the algorithm used. The 32-bit result is stored in four registers RES3:RES0. To account for the sign bits of the arguments, each argument pairs most significant bit (MSb) is tested and the appropriate subtractions are done. EXAMPLE 6-4: MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF MOVFF MOVFF ; MOVFF MULWF 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; ARG1L, WREG ARG2L PRODH, RES1 PRODL, RES0 ARG1H, WREG ARG2H PRODH, RES3 PRODL, RES2 ARG1L, WREG ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, WREG ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, WREG RES2 ARG1H, WREG RES3 EQUATION 6-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L * ARG2H:ARG2L + = (ARG1H * ARG2H * 216) + (ARG1H * ARG2L * 28) (ARG1L * ARG2H * 28) + (ARG1L * ARG2L) + (-1 * ARG2H<7> * ARG1H:ARG1L * 216) (-1 * ARG1H<7> * ARG2H:ARG2L * 216) ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; + MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; MOVFF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC ; BTFSS GOTO MOVFF SUBWF MOVFF SUBWFB ; SIGN_ARG1 BTFSS GOTO MOVFF SUBWF MOVFF SUBWFB ; CONT_CODE : ; ARG1L * ARG2H -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ; ARG1H * ARG2L -> ; PRODH:PRODL ; ; Add cross ; products ; ; ; ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, WREG RES2 ARG2H, WREG RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; 2000 Microchip Technology Inc. Advanced Information DS30475A-page 73 PIC18CXX8 NOTES: DS30475A-page 74 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 7.0 INTERRUPTS The PIC18CXX8 devices have multiple interrupt sources and an interrupt priority feature that allows each interrupt source to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 000008h and the low priority interrupt vector is at 000018h. High priority interrupt events will override any low priority interrupts that may be in progress. There are 13 registers that are used to control interrupt operation. These registers are: * * * * * * * RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3 PIE1, PIE2, PIE3 IPR1, IPR2, IPR3 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PICmicro(R) mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. The PEIE bit (INTCON register) enables/disables all peripheral interrupt sources. The GIE bit (INTCON register) enables/disables all interrupt sources. All interrupts branch to address 000008h in Compatibility mode. When an interrupt is responded to, the Global Interrupt Enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High priority interrupt sources can interrupt a low priority interrupt. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (000008h or 000018h). Once in the interrupt service routine, the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The "return from interrupt" instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INT pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two cycle instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bit or the GIE bit. It is recommended that the Microchip header files supplied with MPLAB be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. Each interrupt source has three bits to control its operation. The functions of these bits are: * Flag bit to indicate that an interrupt event occurred * Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set * Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON register). When interrupt priority is enabled, there are two bits that enable interrupts globally. Setting the GIEH bit (INTCON register) enables all interrupts that have the priority bit set. Setting the GIEL bit (INTCON register) enables all interrupts that have the priority bit cleared. When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address 000008h or 000018h, depending on the priority level. Individual interrupts can be disabled through their corresponding enable bits. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 75 PIC18CXX8 FIGURE 7-1: INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Wake-up if in SLEEP mode Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit Interrupt to CPU Vector to location 0008h GIE/GIEH TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP Additional Peripheral Interrupts High Priority Interrupt Generation Low Priority Interrupt Generation IPEN IPEN GIEL/PEIE IPEN Peripheral Interrupt Flag bit Peripheral Interrupt Enable bit Peripheral Interrupt Priority bit TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE Additional Peripheral Interrupts INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP Interrupt to CPU Vector to Location 0018h TMR1IF TMR1IE TMR1IP XXXXIF XXXXIE XXXXIP PEIE/GIEL DS30475A-page 76 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 7.1 Control Registers 7.1.1 INTCON REGISTERS This section contains the control and status registers. The INTCON Registers are readable and writable registers, which contain various enable, priority, and flag bits. REGISTER 7-1: INTCON REGISTER R/W-0 bit 7 R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF bit 0 GIE/GIEH PEIE/GIEL bit 7 GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all un-masked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high priority interrupts 0 = Disables all high priority interrupts bit 6 PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low priority peripheral interrupts 0 = Disables all priority peripheral interrupts bit 5 TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software by reading PORTB) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 77 PIC18CXX8 REGISTER 7-2: INTCON2 REGISTER R/W-1 RBPU bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 INTEDG0 R/W-1 INTEDG1 R/W-1 INTEDG2 R/W-1 R/W-1 R/W-1 INT3IP R/W-1 RBIP bit 0 INTEDG3 TMR0IP bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. DS30475A-page 78 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 7-3: INTCON3 REGISTER R/W-1 INT2IP bit 7 bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-1 INT1IP R/W-0 INT3IE R/W-0 INT2IE R/W-0 INT1IE R/W-0 INT3IF R/W-0 INT2IF R/W-0 INT1IF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows software polling. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 79 PIC18CXX8 7.1.2 PIR REGISTERS 7.1.3 PIE REGISTERS The Peripheral Interrupt Request (PIR) registers contain the individual flag bits for the peripheral interrupts (Register 7-5). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON register). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt, and after servicing that interrupt. The Peripheral Interrupt Enable (PIE) registers contain the individual enable bits for the peripheral interrupts (Register 7-5). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN is clear, the PEIE bit must be set to enable any of these peripheral interrupts. 7.1.4 IPR REGISTERS The Interrupt Priority (IPR) registers contain the individual priority bits for the peripheral interrupts (Register 7-7). Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). The operation of the priority bits requires that the Interrupt Priority Enable bit (IPEN) be set. 7.1.5 RCON REGISTER The Reset Control (RCON) register contains the bit that is used to enable prioritized interrupts (IPEN). REGISTER 7-4: RCON REGISTER R/W-0 IPEN bit 7 R/W-0 LWRT U-0 -- R/W-1 RI R/W-1 TO R/W-1 PD R/W-0 POR R/W-0 BOR bit 0 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (16CXXX compatibility mode) LWRT: Long Write Enable For details of bit operation see Register 4-3 Unimplemented: Read as '0' RI: RESET Instruction Flag bit For details of bit operation see Register 4-3 TO: Watchdog Time-out Flag bit For details of bit operation see Register 4-3 PD: Power-down Detection Flag bit For details of bit operation see Register 4-3 POR: Power-on Reset Status bit For details of bit operation see Register 4-3 BOR: Brown-out Reset Status bit For details of bit operation see Register 4-3 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 80 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 7-5: PIR1 PIR REGISTERS R/W-0 PSPIF bit 7 U-0 R/W-0 CMIF U-0 -- U-0 -- R/W-0 BCLIF R/W-0 LVDIF R/W-0 TMR3IF R/W-0 ADIF R-0 RCIF R-0 TXIF R/W-0 SSPIF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 R/W-0 CCP2IF bit 0 R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF R/W-0 TXB0IF R/W-0 RXB1IF R/W-0 RXB0IF bit 0 PIR2 bit 7 -- R/W-0 PIR3 IRXIF bit 7 PIR1 bit 7 PSPIF: Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer, RCREG, is full (cleared when RCREG is read) 0 = The USART receive buffer is empty TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer, TXREG, is empty (cleared when TXREG is written) 0 = The USART transmit buffer is full SSPIF: Master Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 81 PIC18CXX8 REGISTER 7-5: PIR2 bit 7 bit 6 PIR REGISTERS (CONT'D) Unimplemented: Read as'0' CMIF: Comparator Interrupt Flag bit 1 = Comparator input has changed 0 = Comparator input has not changed Unimplemented: Read as'0' BCLIF: Bus Collision Interrupt Flag bit 1 = A Bus Collision occurred (must be cleared in software) 0 = No Bus Collision occurred LVDIF: Low Voltage Detect Interrupt Flag bit 1 = A low voltage condition occurred (must be cleared in software) 0 = The device voltage is above the Low Voltage Detect trip point TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow CCP2IF: CCPx Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 5-4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 82 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 7-5: PIR3 bit 7 PIR REGISTERS (CONT'D) IRXIF: Invalid Message Received Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = An invalid message has not occurred on the CAN bus WAKIF: Bus Activity Wake-up Interrupt Flag bit 1 = Activity on the CAN bus has occurred 0 = Activity on the CAN bus has not occurred ERRIF: CAN Bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = An error has not occurred in the CAN module TXB2IF: Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 2 has not completed transmission of a message TXB1IF: Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message, and may be reloaded 0 = Transmit Buffer 0 has not completed transmission of a message RXB1IF: Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message RXB0IF: Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 83 PIC18CXX8 REGISTER 7-6: PIE1 PIE REGISTERS R/W-0 PSPIE bit 7 U-0 R/W-0 CMIE U-0 -- U-0 -- R/W-0 BCLIE R/W-0 LVDIE R/W-0 TMR3IE R/W-0 ADIE R/W-0 RCIE R/W-0 TXIE R/W-0 SSPIE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 R/W-0 CCP2IE bit 0 R/W-1 WAKIE R/W-1 ERRIE R/W-1 TXB2IE R/W-1 TXB1IE R/W-1 TXB0IE R/W-1 RXB1IE R/W-1 RXB0IE bit 0 PIE2 -- bit 7 R/W-1 PIE3 IVRE bit 7 PIE1 bit 7 PSPIE: Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt SSPIE: Master Synchronous Serial Port Interrupt Enable bit 1 = Enables the MSSP interrupt 0 = Disables the MSSP interrupt CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 84 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 7-6: PIE2 bit 7 bit 6 PIE REGISTERS (CONT'D) Unimplemented: Read as '0' CMIE: Comparator Interrupt Enable bit 1 = Enables the comparator interrupt 0 = Disables the comparator interrupt Unimplemented: Read as '0' BCLIE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled LVDIE: Low-voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enables the TMR3 overflow interrupt 0 = Disables the TMR3 overflow interrupt CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt IVRE: Invalid CAN Message Received Interrupt Enable bit 1 = Enables the Invalid CAN Message Received Interrupt 0 = Disables the Invalid CAN Message Received Interrupt WAKIE: Bus Activity Wake-up Interrupt Enable bit 1 = Enables the Bus Activity Wake-Up Interrupt 0 = Disables the Bus Activity Wake-Up Interrupt ERRIE: CAN Bus Error Interrupt Enable bit 1 = Enables the CAN Bus Error Interrupt 0 = Disables the CAN Bus Error Interrupt TXB2IE: Transmit Buffer 2 Interrupt Enable bit 1 = Enables the Transmit Buffer 2 Interrupt 0 = Disables the Transmit Buffer 2 Interrupt TXB1IE: Transmit Buffer 1 Interrupt Enable bit 1 = Enables the Transmit Buffer 1 Interrupt 0 = Disables the Transmit Buffer 1 Interrupt TXB0IE: Transmit Buffer 0 Interrupt Enable bit 1 = Enables the Transmit Buffer 0 Interrupt 0 = Disables the Transmit Buffer 0 Interrupt RXB1IE: Receive Buffer 1 Interrupt Enable bit 1 = Enables the Receive Buffer 1 Interrupt 0 = Disables the Receive Buffer 1 Interrupt RXB0IE: Receive Buffer 0 Interrupt Enable bit 1 = Enables the Receive Buffer 0 Interrupt 0 = Disables the Receive Buffer 0 Interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-4 bit 3 bit 2 bit 1 bit 0 PIE3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 85 PIC18CXX8 REGISTER 7-7: IPR1 IPR REGISTERS R/W-1 PSPIP bit 7 U-0 R/W-1 CMIP U-0 -- U-0 -- R/W-1 BCLIP R/W-1 LVDIP R/W-1 TMR3IP R/W-1 ADIP R/W-1 RCIP R/W-1 TXIP R/W-1 SSPIP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 R/W-1 CCP2IP bit 0 R/W-1 WAKIP R/W-1 ERRIP R/W-1 TXB2IP R/W-1 TXB1IP R/W-1 TXB0IP R/W-1 RXB1IP R/W-1 RXB0IP bit 0 IPR2 -- bit 7 R/W-1 IPR3 IVRP bit 7 IPR1 bit 7 PSPIP: Parallel Slave Port Read/Write Interrupt Priority bit 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RCIP: USART Receive Interrupt Priority bit 1 = High priority 0 = Low priority TXIP: USART Transmit Interrupt Priority bit 1 = High priority 0 = Low priority SSPIP: Master Synchronous Serial Port Interrupt Priority bit 1 = High priority 0 = Low priority CCP1IP: CCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 86 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 7-7: IPR2 bit 7 bit 6 IPR REGISTERS (CONT'D) Unimplemented: Read as '0' CMIP: Comparator Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as '0' BCLIP: Bus Collision Interrupt Priority bit 1 = High priority 0 = Low priority LVDIP: Low Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: CCP2 Interrupt Priority bit 1 = High priority 0 = Low priority IVRP: Invalid Message Received Interrupt Priority bit 1 = High priority 0 = Low priority WAKIP: Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN Bus Error Interrupt Priority bit 1 = High priority 0 = Low priority TXB2IP: Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority TXB0IP: Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority RXB1IP: Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority RXB0IP: Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 5-4 bit 3 bit 2 bit 1 bit 0 IPR3 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 87 PIC18CXX8 7.1.6 INT INTERRUPTS External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2, and RB3/INT3 pins are edge triggered: either rising if the corresponding INTEDGx bit is set in the INTCON2 register, or falling, if the INTEDGx bit is clear. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit INTxIF is set. This interrupt can be disabled by clearing the corresponding enable bit INTxIE. Flag bit INTxIF must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1, INT2, and INT3) can wake-up the processor from SLEEP, if bit INTxIE was set prior to going into SLEEP. If the global interrupt enable bit GIE is set, the processor will branch to the interrupt vector following wake-up. Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the interrupt priority bits INT1IP (INTCON3 register), INT3IP (INTCON3 register), and INT2IP (INTCON2 register). There is no priority bit associated with INT0; it is always a high priority interrupt source. 7.1.7 TMR0 INTERRUPT TMR0H:TMR0L registers will set flag bit TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit TMR0IE (INTCON register). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit TMR0IP (INTCON2 register). See Section 10.0 for further details on the Timer0 module. 7.1.8 PORTB INTERRUPT-ON-CHANGE An input change on PORTB<7:4> sets flag bit RBIF (INTCON register). The interrupt can be enabled/ disabled by setting/clearing enable bit RBIE (INTCON register). Interrupt priority for PORTB interrupton-change is determined by the value contained in the interrupt priority bit RBIP (INTCON2 register). 7.2 Context Saving During Interrupts In 8-bit mode (which is the default), an overflow (FFh 00h) in the TMR0 register will set flag bit TMR0IF. In 16-bit mode, an overflow (FFFFh 0000h) in the During an interrupt, the return PC value is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the fast return stack. If a fast return from interrupt is not used (See Section 4.3), the user may need to save the WREG, STATUS and BSR registers in software. Depending on the user's application, other registers may also need to be saved. Example 7-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine. EXAMPLE 7-1: SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in Low Access bank ; STATUS_TEMP located anywhere ; BSR located anywhere MOVWF W_TEMP MOVFF STATUS, STATUS_TEMP MOVFF BSR, BSR_TEMP ; ; USER ISR CODE ; MOVFF BSR_TEMP, BSR MOVF W_TEMP, W MOVFF STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS DS30475A-page 88 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.0 I/O PORTS EXAMPLE 8-1: CLRF PORTA INITIALIZING PORTA ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTA by clearing output data latches Alternate method to clear output data latches Configure A/D for digital inputs Value used to initialize data direction Set RA3:RA0 as inputs RA5:RA4 as outputs Depending on the device selected, there are up to eleven ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: * TRIS register (Data Direction register) * PORT register (reads the levels on the pins of the device) * LAT register (output latch) The data latch (LAT register) is useful for read-modify-write operations on the value that the I/O pins are driving. CLRF LATA MOVLW MOVWF MOVLW 0x07 ADCON1 0xCF MOVWF TRISA FIGURE 8-1: 8.1 PORTA, TRISA and LATA Registers RA3:RA0 AND RA5 PINS BLOCK DIAGRAM PORTA is a 6-bit wide, bi-directional port. The corresponding Data Direction register is TRISA. Setting a TRISA bit (=1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISA bit (=0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). On a Power-on Reset, these pins are configured as inputs and read as '0'. Reading the PORTA register reads the status of the pins, whereas writing to it will write to the port latch. Read-modify-write operations on the LATA register, reads and writes the latched output value for PORTA. The RA4 pin is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full CMOS output drivers. The other PORTA pins are multiplexed with analog inputs and the analog VREF+ and VREF- inputs. The operation of each pin is selected by clearing/setting the control bits in the ADCON1 register (A/D Control Register1). On a Power-on Reset, these pins are configured as analog inputs and read as '0'. The TRISA register controls the direction of the RA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. RD LATA Data Bus D Q VDD WR LATA or WR PORTA CK Q P I/O Pin(1) Data Latch D Q N WR TRISA CK Q TRIS Latch VSS Analog Input Mode RD TRISA Q D TTL Input Buffer EN RD PORTA SS Input (RA5 only) To A/D Converter and LVD Modules Note 1: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 89 PIC18CXX8 FIGURE 8-2: RA4/T0CKI PIN BLOCK DIAGRAM FIGURE 8-3: ECRA6 or RCRA6 Enable Data Bus RD LATA Data Bus WR LATA or WR PORTA RD LATA D Q RA6 BLOCK DIAGRAM D CK Q Q VDD Data Latch D Q N VSS Schmitt Trigger Input Buffer I/O Pin (1) WR LATA or WR PORTA CK Q P Data Latch D WR TRISA Q N I/O Pin(1) WR TRISA CK Q TRIS Latch CK Q ECRA6 or RCRA6 Enable VSS TRIS Latch RD TRISA Data Bus Q D RD TRISA EN EN RD PORTA Data Bus TMR0 Clock Input Note 1: I/O pin has diode protection to VSS only. RD PORTA Note 1: TTL Input Buffer Q D EN I/O pins have diode protection to VDD and VSS. TABLE 8-1: Name RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI PORTA FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer TTL TTL TTL TTL ST/OD TTL TTL Input/output or analog input. Input/output or analog input. Input/output or analog input or VREF-. Input/output or analog input or VREF+. Input/output or external clock input for Timer0 output is open drain type. Input/output or slave select input for synchronous serial port or analog input, or low voltage detect input. OSC2 or clock output or I/O pin. Function RA5/SS/AN4/LVDIN OSC2/CLKO/RA6 Legend: TTL = TTL input, ST = Schmitt Trigger input, OD = Open Drain TABLE 8-2: Name PORTA LATA TRISA ADCON1 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 -- -- -- -- Bit 6 RA6 Bit 5 RA5 Bit 4 RA4 Bit 3 RA3 Bit 2 RA2 Bit 1 RA1 Bit 0 RA0 Value on POR, BOR Value on all other RESETS -x0x 0000 -uuu uuuu -xxx xxxx -uuu uuuu -111 1111 -111 1111 Latch A Data Output Register PORTA Data Direction Register -- VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 --uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. DS30475A-page 90 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.2 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide bi-directional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (=1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISB bit (=0) will make the corresponding PORTB pin an output ( i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATB register read and write the latched output value for PORTB. Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit RBPU (INTCON2 register). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a Power-on Reset. Four of PORTB's pins, RB7:RB4, have an interrupt-on-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB7:RB4 pin configured as an output is excluded from the interrupt-on-change comparison). The input pins (of RB7:RB4) are compared with the old value latched on the last read of PORTB. The "mismatch" outputs of RB7:RB4 are OR'd together to generate the RB Port Change Interrupt with flag bit RBIF (INTCON register). This interrupt can wake the device from SLEEP. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) Any read or write of PORTB (except with the MOVFF instruction). This will end the mismatch condition. Clear flag bit RBIF. EXAMPLE 8-2: CLRF PORTB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RB3:RB0 as inputs RB5:RB4 as outputs RB7:RB6 as inputs CLRF LATB MOVLW 0xCF MOVWF TRISB b) A mismatch condition will continue to set flag bit RBIF. Reading PORTB will end the mismatch condition and allow flag bit RBIF to be cleared. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt on change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. FIGURE 8-4: RB7:RB4 PINS BLOCK DIAGRAM VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O pin(1) RBPU(2) Data Bus WR LATB or WR PORTB FIGURE 8-5: RBPU(2) RB3:RB0 PINS BLOCK DIAGRAM VDD Weak P Pull-up Data Latch D CK TRIS Latch D Q Q I/O Pin(1) Data Bus WR TRISB CK TTL Input Buffer ST Buffer WR Port RD TRISB WR TRIS RD LATB Q RD PORTB Set RBIF Latch D EN Q1 CK TTL Input Buffer RD TRIS Q D EN From other RB7:RB4 pins Q D RD PORTB EN Q3 RBx/INTx RD Port Schmitt Trigger Buffer RBx/INTx Note 1: 2: I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). Note 1: 2: RD Port I/O pins have diode protection to VDD and VSS. To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (INTCON2 register). 2000 Microchip Technology Inc. Advanced Information DS30475A-page 91 PIC18CXX8 TABLE 8-3: Name RB0/INT0 RB1/INT1 RB2/INT2 RB3/INT3 RB4 RB5 RB6 RB7 PORTB FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer TTL/ST(1) TTL/ST(1) TTL/ST(1) TTL/ST(1) TTL TTL TTL/ST(2) TTL/ST(2) Function Input/output pin or external interrupt 0 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 1 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 2 input. Internal software programmable weak pull-up. Input/output pin or external interrupt 3 input. Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming clock. Input/output pin (with interrupt-on-change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in Serial Programming mode. TABLE 8-4: Name Bit 7 SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 0000 000x 1111 1111 1100 0000 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 000u 1111 1111 1100 0000 PORTB LATB TRISB INTCON INTCON2 INTCON3 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 LATB Data Output Register PORTB Data Direction Register GIE/ GIEH RBPU INT2IP PEIE/ GIEL INTEDG0 INT1IP TMR0IE INTEDG1 INT3IE Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30475A-page 92 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.3 PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISC bit (=0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATC register, read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (Table 8-5). PORTC pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRIS bits for each PORTC pin. Some peripherals override the TRIS bit to make a pin an output, while other peripherals override the TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. The pin override value is not loaded into the TRIS register. This allows read-modify-write of the TRIS register, without concern due to peripheral overrides. EXAMPLE 8-3: CLRF PORTC INITIALIZING PORTC ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTC by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RC3:RC0 as inputs RC5:RC4 as outputs RC7:RC6 as inputs CLRF LATC MOVLW 0xCF MOVWF TRISC FIGURE 8-6: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT OVERRIDE) Peripheral Out Select Peripheral Data Out 0 1 VDD P RD LATC Data Bus WR LATC or WR PORTC D CK Q Q I/O Pin N TRIS Override Data Latch D Q WR TRISC VSS CK Q TRIS Latch Peripheral Enable RD TRISC Q D EN Schmitt Trigger RD PORTC Peripheral Data In TRIS OVERRIDE Pin RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 Note: Override Yes Yes No Yes Yes Yes Yes Yes Peripheral Timer1 OSC for Timer1/Timer3 Timer1 OSC for Timer1/Timer3 -- SPI/I2C Master Clock I2C Data Out SPI Data Out USART Async Xmit, Sync Clock USART Sync Data Out I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 93 PIC18CXX8 TABLE 8-5: Name RC0/T1OSO/T13CKI RC1/T1OSI RC2/CCP1 RC3/SCK/SCL RC4/SDI/SDA RC5/SDO RC6/TX/CK RC7/RX/DT PORTC FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST ST ST ST ST ST ST ST Function Input/output port pin or Timer1 oscillator output or Timer1/Timer3 clock input. Input/output port pin or Timer1 oscillator input. Input/output port pin or Capture1 input/Compare1 output/PWM1 output. Input/output port pin or Synchronous Serial clock for SPI/I2C. Input/output port pin or SPI Data in (SPI mode) or Data I/O (I2C mode). Input/output port pin or Synchronous Serial Port data output. Input/output port pin Addressable USART Asynchronous Transmit or Addressable USART Synchronous Clock. Input/output port pin Addressable USART Asynchronous Receive or Addressable USART Synchronous Data. Legend: ST = Schmitt Trigger input TABLE 8-6: Name SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 PORTC LATC TRISC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 LATC Data Output Register PORTC Data Direction Register Legend: x = unknown, u = unchanged DS30475A-page 94 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.4 PORTD, TRISD and LATD Registers FIGURE 8-7: PORTD is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (=1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISD bit (=0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATD register reads and writes the latched output value for PORTD. PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide microprocessor port (parallel slave port), by setting control bit PSPMODE (PSPCON register). In this mode, the input buffers are TTL. See Section 9.0 for additional information on the Parallel Slave Port (PSP). PORTD BLOCK DIAGRAM IN I/O PORT MODE RD LATD Data Bus WR LATD or WR PORTD D Q I/O Pin CK Data Latch D WR TRISD Q Schmitt Trigger Input Buffer CK TRIS Latch RD TRISD Q D EN EN EXAMPLE 8-4: CLRF PORTD INITIALIZING PORTD ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD3:RD0 as inputs RD5:RD4 as outputs RD7:RD6 as inputs RD PORTD CLRF LATD Note: I/O pins have diode protection to VDD and VSS. MOVLW 0xCF MOVWF TRISD 2000 Microchip Technology Inc. Advanced Information DS30475A-page 95 PIC18CXX8 TABLE 8-7: Name RD0/PSP0 RD1/PSP1 RD2/PSP2 RD3/PSP3 RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 PORTD FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 Buffer Type ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL(1) ST/TTL (1) Function Input/output port pin or parallel slave port bit0. Input/output port pin or parallel slave port bit1. Input/output port pin or parallel slave port bit2. Input/output port pin or parallel slave port bit3. Input/output port pin or parallel slave port bit4. Input/output port pin or parallel slave port bit5. Input/output port pin or parallel slave port bit6. Input/output port pin or parallel slave port bit7. ST/TTL(1) ST/TTL(1) Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 8-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Value on POR, BOR xxxx xxxx xxxx xxxx 1111 1111 -- -- -- -- 0000 ---Value on all other RESETS uuuu uuuu uuuu uuuu 1111 1111 0000 ---- Name PORTD LATD TRISD PSPCON Bit 7 RD7 Bit 6 RD6 Bit 5 RD5 Bit 4 RD4 Bit 3 RD3 Bit 2 RD2 Bit 1 RD1 Bit 0 RD0 LATD Data Output Register PORTD Data Direction Register IBF OBF IBOV PSPMODE Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PORTD. DS30475A-page 96 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.5 PORTE, TRISE and LATE Registers EXAMPLE 8-5: CLRF PORTE INITIALIZING PORTE ; ; ; ; ; ; ; ; ; ; ; Initialize PORTE by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RE1:RE0 as inputs RE7:RE2 as outputs PORTE is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISE. Setting a TRISE bit (=1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISE bit (=0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATE register reads and writes the latched output value for PORTE. PORTE is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. PORTE is multiplexed with several peripheral functions (Table 8-9). CLRF LATE MOVLW 0x03 MOVWF TRISE FIGURE 8-8: PORTE BLOCK DIAGRAM Peripheral Out Select Peripheral Data Out 0 1 VDD P RD LATE Data Bus WR LATE or WR PORTE D CK Q Q I/O Pin(1) N TRIS Override Data Latch D Q WR TRISE VSS CK Q TRIS Latch Peripheral Enable RD TRISE Q D EN Schmitt Trigger RD PORTE Peripheral Data In TRIS OVERRIDE Pin RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 Note 1: Override Yes Yes Yes No No No No No Peripheral PSP PSP PSP -- -- -- -- -- I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 97 PIC18CXX8 TABLE 8-9: Name RE0/RD RE1/WR RE2/CS RE3 RE4 RE5 RE6 PORTE FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST/TTL ST/TTL ST/TTL ST ST ST ST (1) (1) (1) Function Input/output port pin or Read control input in Parallel Slave Port mode. Input/output port pin or Write control input in Parallel Slave Port mode. Input/output port pin or Chip Select control input in Parallel Slave Port mode. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. RE7/CCP2 bit7 ST Input/output port pin or Capture 2 input/Compare 2 output. Legend: ST = Schmitt Trigger input, TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port mode. TABLE 8-10: Name TRISE PORTE LATE PSPCON Bit 7 SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx -- -- 0000 ---Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu 0000 ---- PORTE Data Direction Control Register Read PORTE pin/Write PORTE Data Latch Read PORTE Data Latch/Write PORTE Data Latch IBF OBF IBOV PSPMODE -- -- Legend: x = unknown, u = unchanged DS30475A-page 98 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.6 PORTF, LATF, and TRISF Registers EXAMPLE 8-6: CLRF PORTF INITIALIZING PORTF ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTF by clearing output data latches Alternate method to clear output data latches Turn off comparators Set PORTF as digital I/O Value used to initialize data direction Set RF3:RF0 as inputs RF5:RF4 as outputs RF7:RF6 as inputs PORTF is an 8-bit wide, bi-directional port. The corresponding Data Direction register is TRISF. Setting a TRISF bit (=1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISF bit (=0) will make the corresponding PORTF pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATF register reads and writes the latched output value for PORTF. PORTF is multiplexed with several analog peripheral functions including the A/D converter inputs and comparator inputs, outputs, and voltage reference. Note 1: On a Power-on Reset, the RF6:RF0 pins are configured as inputs and read as '0'. 2: To configure PORTF as digital I/O, turn off comparators and set ADCON1 value. CLRF LATF MOVLW MOVWF MOVLW MOVWF MOVLW 0x07 CMCON 0x0F ADCON1 0xCF MOVWF TRISF FIGURE 8-9: PORTF RF1/AN6/C2OUT, RF2/AN5/C1OUT BLOCK DIAGRAM PORT/Comparator Select Comparator Data Out 0 1 VDD P RD LATF Data Bus WR LATF or WR PORTF D CK Q Q N VSS I/O Pin Data Latch D WR TRISF CK Q Q Analog Input Mode Schmitt Trigger Q D EN TRIS Latch RD TRISF RD PORTF To A/D Converter Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 99 PIC18CXX8 FIGURE 8-10: RF6:RF3 AND RF0 PINS BLOCK DIAGRAM FIGURE 8-11: RF7 PIN BLOCK DIAGRAM RD LATF RD LATF Data Bus D Q VDD WR LATF or WR PORTF CK Q P WR LATF or WR PORTF CK Data Latch D N I/O Pin WR TRISF Q Schmitt Trigger Input Buffer Data Bus D Q I/O pin Data Latch D Q CK TRIS Latch WR TRISF CK Q TRIS Latch VSS Analog Input Mode RD TRISF ST Input Buffer RD TRISF Q D Q D EN EN RD PORTF EN RD PORTF Note: To A/D Converter or Comparator Input Note: I/O pins have diode protection to VDD and VSS. I/O pins have diode protection to VDD and VSS. TABLE 8-11: Name RF0/AN5 PORTF FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST ST ST ST ST ST ST Function Input/output port pin or analog input. Input/output port pin or analog input or comparator 2 output. Input/output port pin or analog input or comparator 1 output. Input/output port pin or analog input or comparator input. Input/output port pin or analog input or comparator input. Input/output port pin or analog input or comparator input or comparator reference output. Input/output port pin or analog input or comparator input. Input/output port pin. RF1/AN6/C2OUT RF2/AN7/C1OUT RF3/AN8 RF4/AN9 RF5/AN10/ CVREF RF6/AN11 RF7 bit7 ST Legend: ST = Schmitt Trigger input TABLE 8-12: Name TRISF PORTF LATF ADCON1 CMCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTF Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx 0000 0000 Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu --00 0000 0000 0000 Bit 7 PORTF Data Direction Control Register Read PORTF pin / Write PORTF Data Latch Read PORTF Data Latch/Write PORTF Data Latch -- C2OUT -- C1OUT VCFG1 VCFG0 PCFG3 PCFG2 PCFG1 PCFG0 --00 0000 C2INV C1INV CIS CM2 CM1 CM0 0000 0000 Legend: x = unknown, u = unchanged DS30475A-page 100 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 8.7 PORTG, LATG, and TRISG Registers EXAMPLE 8-7: CLRF PORTG INITIALIZING PORTG ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTG by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RG1:RG0 as outputs RG2 as input RG4:RG3 as outputs PORTG is a 5-bit wide, bi-directional port. The corresponding Data Direction register is TRISG. Setting a TRISG bit (=1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISG bit (=0) will make the corresponding PORTG pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATG register read and write the latched output value for PORTG. Pins RG0-RG2 on PORTG are multiplexed with the CAN peripheral. Refer to "CAN Module", Section 17.0 for proper settings of TRISG when CAN is enabled. CLRF LATG MOVLW 0x04 MOVWF TRISG FIGURE 8-12: RG0/CANTX0 PIN BLOCK DIAGRAM OPMODE2:OPMODE0=000 TXD ENDRHI 0 RD LATG Data Bus WR PORTG or WR LATG VDD 1 D Q P CK Q Data Latch D Q I/O Pin N WR TRISG CK Q TRIS Latch OPMODE2:OPMODE0 = 000 RD TRISG Q D EN EN VSS Schmitt Trigger RD PORTG Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 101 PIC18CXX8 FIGURE 8-13: RG1/CANTX1 PIN BLOCK DIAGRAM TX1SRC TXD CANCLK 0 1 ENDRHI OPMODE2:OPMODE0=000 TX1EN 0 RD LATG Data Bus WR PORTG or WR LATG VDD 1 D Q Q P CK Data Latch D Q I/O Pin WR TRISG N CK Q TRIS Latch OPMODE2:OPMODE0 = 000 VSS Schmitt Trigger RD TRISG Q D EN EN RD PORTG Note: I/O pins have diode protection to VDD and VSS. FIGURE 8-14: RG2/CANRX PIN BLOCK DIAGRAM FIGURE 8-15: RG4:RG3 PINS BLOCK DIAGRAM RD LATG Data Bus WR LATG or WR PORTG D CK Data Latch RD LATG Data Bus I/O Pin WR LATG or WR PORTG D Q Q I/O Pin CK Data Latch D Q D WR TRISG CK Q Schmitt Trigger Input Buffer WR TRISG CK TRIS Latch TRIS Latch Schmitt Trigger Input Buffer RD TRISG Q D EN EN RD PORTG CANRX Note: I/O pins have diode protection to VDD and VSS. Note: RD PORTG RD TRISG Q D EN EN I/O pins have diode protection to VDD and VSS. DS30475A-page 102 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 8-13: Name RG0/CANTX0 RG1/CANTX1 RG2/CANRX RG3 PORTG FUNCTIONS Bit# bit0 bit1 bit2 bit3 Buffer Type ST ST ST ST Function Input/output port pin or CAN bus transmit output. Input/output port pin or CAN bus complimentary transmit output or CAN bus bit time clock. Input/output port pin or CAN bus receive input. Input/output port pin. Input/output port pin. RG4 bit4 ST Legend: ST = Schmitt Trigger input Note: Refer to "CAN Module", Section 17.0 for usage of CAN pin functions. TABLE 8-14: Name TRISG PORTG LATG CIOCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTG Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR ---1 1111 ---x xxxx ---x xxxx -- -- -- 0000 ---Value on all other RESETS ---1 1111 ---u uuuu ---u uuuu 0000 ---- Bit 7 PORTG Data Direction Control Register Read PORTG pin / Write PORTG Data Latch Read PORTG Data Latch/Write PORTG Data Latch TX1SRC TX1EN ENDRHI CANCAP -- Legend: x = unknown, u = unchanged 2000 Microchip Technology Inc. Advanced Information DS30475A-page 103 PIC18CXX8 8.8 Note: PORTH, LATH, and TRISH Registers This port is available on PIC18C858. EXAMPLE 8-8: CLRF PORTH INITIALIZING PORTH ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTH by clearing output data latches Alternate method to clear output data latches PORTH is a 5-bit wide, bi-directional port available only on the PIC18C858 devices. The corresponding Data Direction register is TRISH. Setting a TRISH bit (=1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISH bit (=0) will make the corresponding PORTH pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATH register read and write the latched output value for PORTH. Pins RH0-RH3 on the PIC18C858 are bi-directional I/O pins with ST input buffers. Pins RH4-RH7 on all devices are multiplexed with A/D converter inputs. Note: On a Power-on Reset, the RH7:RH4 pins are configured as inputs and read as '0'. CLRF LATH MOVLW MOVWF MOVLW 0x0F ADCON1 0xCF MOVWF TRISH Value used to initialize data direction Set RH3:RH0 as inputs RH5:RH4 as outputs RH7:RH6 as inputs FIGURE 8-17: RH7:RH4 PINS BLOCK DIAGRAM FIGURE 8-16: RH3:RH0 PINS BLOCK DIAGRAM RD LATH Data Bus D Q VDD Data Bus WR LATH or WR PORTH RD LATH D CK Q Q VDD P WR LATH or WR PORTH CK Q P Data Latch D Q N I/O Pin Data Latch WR TRISH D Q Q N VSS RD TRISH RD TRISH Q D EN RD PORTH Schmitt Trigger Q D ST Input Buffer I/O Pin CK Q VSS Analog Input Mode TRIS Latch WR TRISH CK TRIS Latch RD PORTH EN Note: I/O pins have diode protection to VDD and VSS. To A/D Converter Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 104 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 8-15: Name RH0 RH1 RH2 RH3 RH4/AN12 RH5/AN13 RH6/AN14 PORTH FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST ST ST ST ST ST ST Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin or analog input channel 12. Input/output port pin or analog input channel 13. Input/output port pin or analog input channel 14. Input/output port pin or analog input channel 15. Function RH7/AN15 bit7 ST Legend: ST = Schmitt Trigger input TABLE 8-16: Name TRISH PORTH LATH ADCON1 Bit 7 SUMMARY OF REGISTERS ASSOCIATED WITH PORTH Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx PCFG1 PCFG0 --00 0000 Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu --00 0000 PORTH Data Direction Control Register Read PORTH pin/Write PORTH Data Latch Read PORTH Data Latch/Write PORTH Data Latch -- -- VCFG1 VCFG0 PCFG3 PCFG2 Legend: x = unknown, u = unchanged, - = unimplemented 2000 Microchip Technology Inc. Advanced Information DS30475A-page 105 PIC18CXX8 8.9 Note: PORTJ, LATJ, and TRISJ Registers This port is available on PIC18C858. EXAMPLE 8-9: CLRF PORTJ INITIALIZING PORTJ ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTJ by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RJ3:RJ0 as inputs RJ5:RJ4 as outputs RJ7:RJ6 as inputs PORTJ is an 8-bit wide, bi-directional port available only on the PIC18C858 devices. The corresponding Data Direction register is TRISJ. Setting a TRISJ bit (=1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISJ bit (=0) will make the corresponding PORTJ pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATJ register read and write the latched output value for PORTJ. PORTJ on the PIC18C858 is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. CLRF LATJ MOVLW 0xCF MOVWF TRISJ FIGURE 8-18: PORTJ BLOCK DIAGRAM RD LATJ Data Bus WR LATJ or WR PORTJ D CK Q VDD Q P Data Latch I/O Pin N D Q WR TRISJ VSS CK Q TRIS Latch RD TRISJ Schmitt Trigger Q D EN RD PORTJ Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 106 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 8-17: Name RJ0 RJ1 RJ2 RJ3 RJ4 RJ5 RJ6 PORTJ FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Function RJ7 bit7 ST/TTL Input/output port pin. Legend: ST = Schmitt Trigger input, TTL = TTL input TABLE 8-18: Name TRISJ PORTJ LATJ SUMMARY OF REGISTERS ASSOCIATED WITH PORTJ Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu Bit 7 Bit 6 Bit 5 PORTJ Data Direction Control Register Read PORTJ pin/Write PORTJ Data Latch Read PORTJ Data Latch/Write PORTJ Data Latch Legend: x = unknown, u = unchanged 2000 Microchip Technology Inc. Advanced Information DS30475A-page 107 PIC18CXX8 8.10 Note: PORTK, LATK, and TRISK Registers This port is available on PIC18C858. FIGURE 8-19: PORTK BLOCK DIAGRAM PORTK is an 8-bit wide, bi-directional port available only on the PIC18C858 devices. The corresponding Data Direction register is TRISK. Setting a TRISK bit (=1) will make the corresponding PORTK pin an input (i.e., put the corresponding output driver in a hi-impedance mode). Clearing a TRISK bit (=0) will make the corresponding PORTK pin an output (i.e., put the contents of the output latch on the selected pin). Read-modify-write operations on the LATK register read and write the latched output value for PORTK. PORTK is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. RD LATK Data Bus WR LATK or WR PORTK D Q I/O Pin CK Data Latch D Q Schmitt Trigger Input Buffer WR TRISK CK TRIS Latch RD TRISK EXAMPLE 8-10: INITIALIZING PORTK CLRF PORTK ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTK by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RK3:RK0 as inputs RK5:RK4 as outputs RK7:RK6 as inputs Q D EN EN CLRF LATK RD PORTK MOVLW 0xCF Note: I/O pins have diode protection to VDD and VSS. MOVWF TRISK TABLE 8-19: Name RK0 RK1 RK2 RK3 RK4 RK5 RK6 PORTK FUNCTIONS Bit# bit0 bit1 bit2 bit3 bit4 bit5 bit6 Buffer Type ST ST ST ST ST ST ST Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Input/output port pin. Function RK7 bit7 ST Legend: ST = Schmitt Trigger input TABLE 8-20: Name TRISK SUMMARY OF REGISTERS ASSOCIATED WITH PORTK Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 1111 1111 xxxx xxxx xxxx xxxx Value on all other RESETS 1111 1111 uuuu uuuu uuuu uuuu Bit 7 Bit 6 PORTK Data Direction Control Register PORTK Read PORTK pin / Write PORTK Data Latch LATK Read PORTK Data Latch/Write PORTK Data Latch Legend: x = unknown, u = unchanged DS30475A-page 108 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 9.0 PARALLEL SLAVE PORT FIGURE 9-1: The Parallel Slave Port is an 8-bit parallel interface for transferring data between the PIC18CXX8 device and an external device. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE (PSPCON register) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin RE0/RD and WR control input pin RE1/WR. It can directly interface to an 8-bit microprocessor data bus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE enables port pin RE0/RD to be the RD input, RE1/WR to be the WR input and RE2/CS to be the CS (chip select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) must be configured as inputs (set). A write to the PSP occurs when both the CS and WR lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. The PORTE I/O pins become control inputs for the microprocessor port when bit PSPMODE (PSPCON Register) is set. In this mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital inputs). In this mode, the input buffers are TTL. Data Bus D Q PORTD AND PORTE BLOCK DIAGRAM (PARALLEL SLAVE PORT) WR LATD or WR PORTD RDx Pin CK Data Latch Q D EN EN TTL RD PORTD RD LATD One bit of PORTD Set Interrupt Flag PSPIF (PIR1<7>) Read TTL RD Chip Select TTL Write TTL CS WR Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 109 PIC18CXX8 REGISTER 9-1: PSPCON REGISTER R-0 IBF bit 7 bit 7 R-0 OBF R/W-0 IBOV R/W-0 PSPMODE U-0 -- U-0 -- U-0 -- U-0 -- bit 0 IBF: Input Buffer Full Status bit 1 = A word has been received and waiting to be read by the CPU 0 = No word has been received OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read IBOV: Input Buffer Overflow Detect bit (in Microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel Slave Port mode 0 = General purpose I/O mode Unimplemented: Read as '0' Legend R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3-0 DS30475A-page 110 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 9-2: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF FIGURE 9-3: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD IBF OBF PSPIF TABLE 9-1: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Value on POR, BOR Value on all other RESETS Name PORTD LATD TRISD PORTE LATE TRISE INTCON PIR1 PIE1 IPR1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port data latch when written; port pins when read LATD Data Output Bits PORTD Data Direction Bits RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE Data Output Bits PORTE Data Direction Bits GIE/ GIEH PSPIF PSPIE PSPIP PEIE/ GIEL ADIF ADIE ADIP TMR0IE RCIF RCIE RCIP INT0IE TXIF TXIE TXIP RBIE SSPIF TMR0IF INT0IF RBIF xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 0000 0000 0000 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 0000 000x 0000 000u CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Parallel Slave Port. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 111 PIC18CXX8 NOTES: DS30475A-page 112 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 10.0 TIMER0 MODULE The Timer0 module has the following features: * Software selectable as an 8-bit or 16-bit timer/counter * Readable and writable * Dedicated 8-bit software programmable prescaler * Clock source selectable to be external or internal * Interrupt on overflow from FFh to 00h in 8-bit mode and FFFFh to 0000h in 16-bit mode * Edge select for external clock Register 10-1 shows the Timer0 Control register (T0CON). Figure 10-1 shows a simplified block diagram of the Timer0 module in 8-bit mode and Figure 10-1 shows a simplified block diagram of the Timer0 module in 16-bit mode. The T0CON register is a readable and writable register that controls all the aspects of Timer0, including the prescale selection. Note: Timer0 is enabled on POR. REGISTER 10-1: T0CON REGISTER R/W-1 TMR0ON bit 7 R/W-1 T08BIT R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 bit 7 TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-bit/16-bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = TImer0 prescaler is NOT assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from prescaler output. T0PS2:T0PS0: Timer0 Prescaler Select bits 111 = 1:256 prescale value 110 = 1:128 prescale value 101 = 1:64 prescale value 100 = 1:32 prescale value 011 = 1:16 prescale value 010 = 1:8 prescale value 001 = 1:4 prescale value 000 = 1:2 prescale value Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3 bit 2-0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 113 PIC18CXX8 FIGURE 10-1: TIMER0 BLOCK DIAGRAM IN 8-BIT MODE Data Bus FOSC/4 0 8 0 1 RA4/T0CKI Pin(2) T0SE Programmable Prescaler 1 Sync with Internal Clocks (2 TCY delay) TMR0L 3 T0PS2, T0PS1, T0PS0 T0CS(1) PSA Set Interrupt Flag bit TMR0IF on Overflow Note 1: 2: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. I/O pins have diode protection to VDD and VSS. FIGURE 10-2: TIMER0 BLOCK DIAGRAM IN 16-BIT MODE FOSC/4 0 0 1 Sync with Internal Clocks (2 TCY delay) TMR0L TMR0 High Byte 8 Set Interrupt Flag bit TMR0IF on Overflow T0CKI Pin(2) T0SE Programmable Prescaler 3 T0PS2, T0PS1, T0PS0 T0CS(1) 1 Read TMR0L Write TMR0L PSA 8 8 TMR0H 8 Data Bus<7:0> Note 1: 2: Upon RESET, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. I/O pins have diode protection to VDD and VSS. DS30475A-page 114 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 10.1 Timer0 Operation 10.2 Prescaler Timer0 can operate as a timer or as a counter. Timer mode is selected by clearing the T0CS bit. In Timer mode, the Timer0 module will increment every instruction cycle (without prescaler). If the TMR0L register is written, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0L register. Counter mode is selected by setting the T0CS bit. In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit (T0SE). Clearing the T0SE bit selects the rising edge. Restrictions on the external clock input are discussed below. When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (TOSC). Also, there is a delay in the actual incrementing of Timer0 after synchronization. An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not readable or writable. The PSA and T0PS2:T0PS0 bits determine the prescaler assignment and prescale ratio. Clearing bit PSA will assign the prescaler to the Timer0 module. When the prescaler is assigned to the Timer0 module, prescale values of 1:2, 1:4, ..., 1:256 are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g. CLRF TMR0, MOVWF TMR0, BSF TMR0, x.... etc.) will clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0, will clear the prescaler count but will not change the prescaler assignment. SWITCHING PRESCALER ASSIGNMENT 10.2.1 The prescaler assignment is fully under software control (i.e., it can be changed "on-the-fly" during program execution). 2000 Microchip Technology Inc. Advanced Information DS30475A-page 115 PIC18CXX8 10.3 Timer0 Interrupt 10.4 16-Bit Mode Timer Reads and Writes The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode or FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF bit. The interrupt can be masked by clearing the TMR0IE bit. The TMR0IF bit must be cleared in software by the Timer0 module interrupt service routine before re-enabling this interrupt. The TMR0 interrupt cannot awaken the processor from SLEEP, since the timer is shut off during SLEEP. Timer0 can be set in 16-bit mode by clearing T0CON T08BIT. Registers TMR0H and TMR0L are used to access 16-bit timer value. TMR0H is not the high byte of the timer/counter in 16-bit mode, but is actually a buffered version of the high byte of Timer0 (refer to Figure 10-1). The high byte of the Timer0 counter/timer is not directly readable nor writable. TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16-bits of Timer0 without having to verify that the read of the high and low byte were valid due to a rollover between successive reads of the high and low byte. A write to the high byte of Timer0 must also take place through the TMR0H buffer register. Timer0 high byte is updated with the contents of buffered value of TMR0H, when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. TABLE 10-1: REGISTERS ASSOCIATED WITH TIMER0 Value on POR, BOR xxxx xxxx 0000 0000 Name TMR0L TMR0H INTCON T0CON TRISA Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on all other RESETS uuuu uuuu 0000 0000 0000 000u 1111 1111 --11 1111 Timer0 Module's Low Byte Register Timer0 Module's High Byte Register GIE/GIEH TMR0ON -- PEIE/GIEL TMR0IE INT0IE T08BIT T0CS T0SE (1) RBIE PSA TMR0IF INT0IF T0PS2 T0PS1 RBIF T0PS0 0000 000x 1111 1111 --11 1111 PORTA Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read as `0'. DS30475A-page 116 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 11.0 TIMER1 MODULE The Timer1 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR1H and TMR1L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * RESET from CCP module special event trigger Register 11-1 shows the Timer1 control register. This register controls the operating mode of the Timer1 module as well as contains the Timer1 oscillator enable bit (T1OSCEN). Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON register). Figure 11-1 is a simplified block diagram of the Timer1 module. Note: Timer1 is disabled on POR. REGISTER 11-1: T1CON REGISTER R/W-0 RD16 bit 7 U-0 -- R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 TMR1CS R/W-0 TMR1ON bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable bit 1 = Enables register Read/Write of TImer1 in one 16-bit operation 0 = Enables register Read/Write of Timer1 in two 8-bit operations bit 6 bit 5-4 Unimplemented: Read as '0' T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3 T1OSCEN: Timer1 Oscillator Enable bit 1 = Timer1 Oscillator is enabled 0 = Timer1 Oscillator is shut off The oscillator inverter and feedback resistor are turned off to eliminate power drain. bit 2 T1SYNC: Timer1 External Clock Input Synchronization Select bit When TMR1CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR1CS = 0: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1 TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T13CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0 TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 117 PIC18CXX8 11.1 Timer1 Operation Timer1 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR1CS (T1CON register). When TMR1CS is clear, Timer1 increments every instruction cycle. When TMR1CS is set, Timer1 increments on every rising edge of the external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer1 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 14.0). FIGURE 11-1: TIMER1 BLOCK DIAGRAM TMR1IF Overflow Interrupt Flag Bit TMR1H CCP Special Event Trigger TMR1 CLR TMR1L TMR1ON On/Off T1OSC T13CKI/T1OSO T1OSI T1OSCEN Enable Oscillator(1) 0 1 T1SYNC Prescaler 1, 2, 4, 8 Synchronize det SLEEP Input Synchronized Clock Input 1 Internal Clock FOSC/4 0 2 T1CKPS1:T1CKPS0 TMR1CS Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. FIGURE 11-2: TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR1H 8 Write TMR1L Read TMR1L TMR1IF Overflow Interrupt Flag bit 8 Timer 1 high byte TMR1 TMR1L 1 TMR1ON On/Off T1OSC T13CKI/T1OSO T1OSCEN Enable Oscillator(1) Fosc/4 Internal Clock 1 Prescaler 1, 2, 4, 8 0 2 TMR1CS T1CKPS1:T1CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This reduces power drain. SLEEP Input Synchronize det T1SYNC Special Event Trigger 0 Synchronized Clock Input 8 T1OSI DS30475A-page 118 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 11.2 Timer1 Oscillator 11.4 A crystal oscillator circuit is built-in between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON register). The oscillator is a low power oscillator rated up to 200 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. Table 11-1 shows the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. Resetting Timer1 using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer1 and start an A/D conversion (if the A/D module is enabled). Note: The special event triggers from the CCP1 module will not set interrupt flag bit TMR1IF (PIR registers). TABLE 11-1: CAPACITOR SELECTION FOR THE ALTERNATE OSCILLATOR Osc Type LP Freq 32 kHz C1 TBD(1) C2 TBD(1) Timer1 must be configured for either timer or Synchronized Counter mode to take advantage of this feature. If Timer1 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer1 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair, effectively becomes the period register for Timer1. Crystal to be Tested: 32.768 kHz Epson C-001R32.768K-A 20 PPM Note 1: Microchip suggests 33 pF as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator, but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. 11.5 Timer1 16-Bit Read/Write Mode 11.3 Timer1 Interrupt The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR registers). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE registers). Timer1 can be configured for 16-bit reads and writes (see Figure 11-2). When the RD16 control bit (T1CON register) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer. This provides the user with the ability to accurately read all 16 bits of Timer1, without having to determine whether a read of the high byte followed by a read of the low byte is valid, due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H buffer register. Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 high byte buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 119 PIC18CXX8 TABLE 11-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR1CS TMR1ON 0-00 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu u-uu uuuu Name Bit 7 Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP INTCON GIE/GIEH PEIE/GIEL PIR1 PIE1 IPR1 TMR1L TMR1H T1CON Legend: PSPIF PSPIE PSPIP ADIF ADIE ADIP Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1 register RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T1SYNC x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. DS30475A-page 120 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 12.0 * * * * * * * TIMER2 MODULE 12.1 Timer2 Operation The Timer2 module timer has the following features: 8-bit timer (TMR2 register) 8-bit period register (PR2) Readable and writable (both registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMR2 match of PR2 SSP module optional use of TMR2 output to generate clock shift Timer2 can be used as the PWM time-base for the PWM mode of the CCP module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON Register). The match output of TMR2 goes through a 4-bit postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit TMR2IF, PIR registers). The prescaler and postscaler counters are cleared when any of the following occurs: * A write to the TMR2 register * A write to the T2CON register * Any device RESET (Power-on Reset, MCLR Reset, Watchdog Timer Reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. Note: Timer2 is disabled on POR. Register 12-1 shows the Timer2 Control register. Timer2 can be shut off by clearing control bit TMR2ON (T2CON register) to minimize power consumption. Figure 12-1 is a simplified block diagram of the Timer2 module. The prescaler and postscaler selection of Timer2 are controlled by this register. REGISTER 12-1: T2CON REGISTER U-0 -- bit 7 R/W-0 TOUTPS3 R/W-0 TOUTPS2 R/W-0 TOUTPS1 R/W-0 TOUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0 bit 7 bit 6-3 Unimplemented: Read as '0' TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale * * * 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 121 PIC18CXX8 12.2 Timer2 Interrupt 12.3 Output of TMR2 The Timer2 module has an 8-bit period register PR2. Timer2 increments from 00h until it matches PR2 and then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is initialized to FFh upon RESET. The output of TMR2 (before the postscaler) is a clock input to the Synchronous Serial Port module, which optionally uses it to generate the shift clock. FIGURE 12-1: TIMER2 BLOCK DIAGRAM TMR2 Output(1) Sets Flag bit TMR2IF FOSC/4 Prescaler 1:1, 1:4, 1:16 2 T2CKPS1:T2CKPS0 TMR2 RESET Comparator EQ PR2 Postscaler 1:1 to 1:16 4 TOUTPS3:TOUTPS0 Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock. TABLE 12-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 0000 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 1111 1111 Name INTCON PIR1 PIE1 IPR1 TMR2 T2CON PR2 Bit 7 GIE/GIEH PSPIF PSPIE PSPIP Bit 6 PEIE/GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 -000 0000 1111 1111 Timer2 module's register -- TOUTPS3 Timer2 Period Register Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer2 module. DS30475A-page 122 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 13.0 TIMER3 MODULE The Timer3 module timer/counter has the following features: * 16-bit timer/counter (Two 8-bit registers: TMR3H and TMR3L) * Readable and writable (both registers) * Internal or external clock select * Interrupt on overflow from FFFFh to 0000h * RESET from CCP module trigger Figure 13-1 is a simplified block diagram of the Timer3 module. Register 13-1 shows the Timer3 Control Register. This register controls the operating mode of the Timer3 module and sets the CCP clock source. Register 11-1 shows the Timer1 Control register. This register controls the operating mode of the Timer1 module, as well as contains the Timer1 oscillator enable bit (T1OSCEN), which can be a clock source for Timer3. Note: Timer3 is disabled on POR. REGISTER 13-1: T3CON REGISTER R/W-0 RD16 bit 7 R/W-0 T3CCP2 R/W-0 T3CKPS1 R/W-0 T3CKPS0 R/W-0 T3CCP1 R/W-0 T3SYNC R/W-0 TMR3CS R/W-0 TMR3ON bit 0 bit 7 RD16: 16-bit Read/Write Mode Enable 1 = Enables register Read/Write of Timer3 in one 16-bit operation 0 = Enables register Read/Write of Timer3 in two 8-bit operations T3CCP2:T3CCP1: Timer3 and Timer1 to CCPx Enable bits 1x = Timer3 is the clock source for compare/capture CCP modules 01 = Timer3 is the clock source for compare/capture of CCP2, Timer1 is the clock source for compare/capture of CCP1 00 = Timer1 is the clock source for compare/capture CCP modules T3CKPS1:T3CKPS0: Timer3 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T3SYNC: Timer3 External Clock Input Synchronization Control bit (Not usable if the system clock comes from Timer1/Timer3) When TMR3CS = 1: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMR3CS = 0: This bit is ignored. Timer3 uses the internal clock when TMR3CS = 0. bit 6,3 bit 5-4 bit 2 bit 1 TMR3CS: Timer3 Clock Source Select bit 1 = External clock input from Timer1 oscillator or T1CKI (on the rising edge after the first falling edge) 0 = Internal clock (Fosc/4) TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 123 PIC18CXX8 13.1 Timer3 Operation Timer3 can operate in one of these modes: * As a timer * As a synchronous counter * As an asynchronous counter The operating mode is determined by the clock select bit, TMR3CS (T3CON register). When TMR3CS = 0, Timer3 increments every instruction cycle. When TMR3CS = 1, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled. When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins become inputs. That is, the TRISC<1:0> value is ignored. Timer3 also has an internal "RESET input". This RESET can be generated by the CCP module (Section 13.0). FIGURE 13-1: TIMER3 BLOCK DIAGRAM TMR3IF Overflow Interrupt Flag bit TMR3H CCP Special Trigger T3CCPx 0 CLR TMR3L TMR3ON on/off T1OSC T1OSO/ T13CKI T1OSI T1OSCEN Fosc/4 Enable Internal Oscillator(1) Clock 1 Prescaler 1, 2, 4, 8 0 2 TMR3CS T3CKPS1:T3CKPS0 Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. SLEEP Input Synchronize det 1 T3SYNC Synchronized Clock Input FIGURE 13-2: TIMER3 BLOCK DIAGRAM CONFIGURED IN 16-BIT READ/WRITE MODE Data Bus<7:0> 8 TMR3H 8 Write TMR3L Read TMR3L TMR3IF Overflow Interrupt Flag bit 8 TMR3H TMR3 TMR3L CLR 1 To Timer1 Clock Input T1OSO/ T13CKI T1OSC 1 T1OSCEN Enable Oscillator(1) FOSC/4 Internal Clock Prescaler 1, 2, 4, 8 0 2 T3CKPS1:T3CKPS0 TMR3CS SLEEP Input TMR3ON On/Off T3SYNC Synchronize det CCP Special Trigger T3CCPx 0 Synchronized Clock Input 8 T1OSI Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30475A-page 124 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 13.2 Timer1 Oscillator 13.4 The Timer1 oscillator may be used as the clock source for Timer3. The Timer1 oscillator is enabled by setting the T1OSCEN bit (T1CON Register). The oscillator is a low power oscillator rated up to 200 kHz. Refer to "Timer1 Module", Section 11.0 for Timer1 oscillator details. Resetting Timer3 Using a CCP Trigger Output If the CCP module is configured in Compare mode to generate a "special event trigger" (CCP1M3:CCP1M0 = 1011), this signal will reset Timer3. Note: The special event triggers from the CCP module will not set interrupt flag bit TMR3IF (PIR registers). 13.3 Timer3 Interrupt The TMR3 Register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR3 Interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit TMR3IF (PIR Registers). This interrupt can be enabled/disabled by setting/clearing TMR3 interrupt enable bit TMR3IE (PIE Registers). Timer3 must be configured for either timer or Synchronized Counter mode to take advantage of this feature. If Timer3 is running in Asynchronous Counter mode, this RESET operation may not work. In the event that a write to Timer3 coincides with a special event trigger from CCP1, the write will take precedence. In this mode of operation, the CCPR1H:CCPR1L registers pair becomes the period register for Timer3. Refer to "Capture/Compare/PWM (CCP) Modules", Section 14.0 for CCP details. TABLE 13-1: Name INTCON PIR2 PIE2 IPR2 TMR3L TMR3H T1CON T3CON Legend: Bit 7 GIE/ GIEH -- -- -- REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER Bit 6 PEIE/ GIEL CMIF CMIE CMIP Bit 5 TMR0IE -- -- -- Bit 4 INT0IE -- -- -- Bit 3 RBIE BCLIF BCLIE BCLIP Bit 2 TMR0IF LVDIF LVDIE LVDIP Bit 1 INT0IF TMR3IF TMR3IE TMR3IP Bit 0 RBIF CCP2IF CCP2IE CCP2IP Value on POR, BOR 0000 000x -0-- 0000 -0-- 0000 -0-- 0000 xxxx xxxx xxxx xxxx Value on all other RESETS 0000 000u -0-- 0000 -0-- 0000 -0-- 0000 uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu Holding register for the Least Significant Byte of the 16-bit TMR3 register Holding register for the Most Significant Byte of the 16-bit TMR3 register RD16 RD16 -- T1CKPS1 T1CKPS0 T1OSCEN T3CCP1 T1SYNC T3SYNC T3CCP2 T3CKPS1 T3CKPS0 TMR1CS TMR1ON 0-00 0000 TMR3CS TMR3ON 0000 0000 x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the Timer1 module. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 125 PIC18CXX8 NOTES: DS30475A-page 126 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 14.0 CAPTURE/COMPARE/PWM (CCP) MODULES Section 17.0 for CAN operation.) Therefore, operation of a CCP module in the following sections is described with respect to CCP1. Table 14-2 shows the interaction of the CCP modules. Register 14-1 shows the CCPx Control registers (CCPxCON). For the CCP1 module, the register is called CCP1CON and for the CCP2 module, the register is called CCP2CON. Each CCP (Capture/Compare/PWM) module contains a 16-bit register that can operate as a 16-bit capture register, as a 16-bit compare register, or as a PWM Duty Cycle register. Table 14-1 shows the timer resources of the CCP module modes. The operation of CCP1 is identical to that of CCP2, with the exception of the special event trigger and the CAN message timestamp received. (Refer to "CAN Module", REGISTER 14-1: CCP1CON REGISTER CCP2CON REGISTER U-0 CCP1CON -- bit 7 U-0 CCP2CON -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' DCxB1:DCxB0: PWM Duty Cycle bit1 and bit0 Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs (bit1 and bit0) of the 10-bit PWM duty cycle. The upper eight bits (DCx9:DCx2) of the duty cycle are found in CCPRxL. bit 3-0 CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = Capture/Compare/PWM off (resets CCPx module) Reserved Compare mode, toggle output on match (CCPxIF bit is set) Capture mode, CAN message received (CCP1 only) Capture mode, every falling edge Capture mode, every rising edge Capture mode, every 4th rising edge Capture mode, every 16th rising edge Compare mode, Initialize CCP pin Low, on compare match force CCP pin High (CCPIF bit is set) Compare mode, Initialize CCP pin High, on compare match force CCP pin Low (CCPIF bit is set) Compare mode, Generate software interrupt on compare match (CCPIF bit is set, CCP pin is unaffected) Compare mode, Trigger special event (CCPIF bit is set, reset TMR1 or TMR3) PWM mode U-0 -- R/W-0 DC2B1 R/W-0 DC2B0 R/W-0 CCP2M3 R/W-0 CCP2M2 R/W-0 CCP2M1 U-0 -- R/W-0 DC1B1 R/W-0 DC1B0 R/W-0 CCP1M3 R/W-0 CCP1M2 R/W-0 CCP1M1 R/W-0 CCP1M0 bit 0 R/W-0 CCP2M0 bit 0 1011 = 11xx = Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 127 PIC18CXX8 14.1 CCP1 Module 14.3 Capture Mode Capture/Compare/PWM Register1 (CCPR1) is comprised of two 8-bit registers: CCPR1L (low byte) and CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on pin RC2/CCP1. An event is defined as: * * * * every falling edge every rising edge every 4th rising edge every 16th rising edge 14.2 CCP2 Module Capture/Compare/PWM Register2 (CCPR2) is comprised of two 8-bit registers: CCPR2L (low byte) and CCPR2H (high byte). The CCP2CON register controls the operation of CCP2. All are readable and writable. TABLE 14-1: CCP MODE - TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2 CCP Mode Capture Compare PWM An event is selected by control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). When a capture is made, the interrupt request flag bit CCP1IF (PIR registers) is set. It must be cleared in software. If another capture occurs before the value in register CCPR1 is read, the old captured value will be lost. 14.3.1 CCP PIN CONFIGURATION In Capture mode, the RC2/CCP1 pin should be configured as an input by setting the TRISC<2> bit. Note: If the RC2/CCP1 is configured as an output, a write to the port can cause a capture condition. TIMER1/TIMER3 MODE SELECTION 14.3.2 The timers used with the capture feature (either Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer used with each CCP module is selected in the T3CON register. TABLE 14-2: Capture Capture Compare PWM PWM PWM INTERACTION OF TWO CCP MODULES Interaction TMR1 or TMR3 time-base. Time-base can be different for each CCP. The compare could be configured for the special event trigger, which clears either TMR1 or TMR3, depending upon which time-base is used. The compare(s) could be configured for the special event trigger, which clears TMR1 or TMR3 depending upon which time-base is used. The PWMs will have the same frequency and update rate (TMR2 interrupt). None None Capture Compare Compare PWM Capture Compare CCPx Mode CCPy Mode DS30475A-page 128 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 14.3.3 SOFTWARE INTERRUPT 14.3.5 CAN MESSAGE RECEIVED When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE registers) clear to avoid false interrupts and should clear the flag bit CCP1IF, following any such change in operating mode. 14.3.4 CCP PRESCALER The CAN capture event occurs when a message is received in either receive buffer. The CAN module provides a rising edge to the CCP module to cause a capture event. This feature is provided to time-stamp the received CAN messages. There are four prescaler settings, specified by bits CCP1M3:CCP1M0. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any RESET will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 14-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the "false" interrupt. EXAMPLE 14-1: CHANGING BETWEEN CAPTURE PRESCALERS CLRF MOVLW CCP1CON, F ; Turn CCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and CCP ON CCP1CON ; Load CCP1CON with ; this value MOVWF FIGURE 14-1: CAPTURE MODE OPERATION BLOCK DIAGRAM CCP1 Pin Prescaler / 1, 4, 16 RXB0IF or RXB1IF CCP1CON<3:0> and edge detect T3CCP2 TMR3H Set Flag bit CCP1IF T3CCP2 TMR3 Enable CCPR1H TMR1 Enable TMR1H CCP1M3:CCP1M0 Q's Set Flag bit CCP2IF T3CCP1 T3CCP2 Prescaler / 1, 4, 16 CCP2 Pin and edge detect TMR3H TMR3 Enable CCPR2H TMR1 Enable T3CCP2 T3CCP1 TMR1H TMR1L CCPR2L TMR3L TMR1L CCPR1L TMR3L CCP2M3:CCP2M0 Q's Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 129 PIC18CXX8 14.4 Compare Mode 14.4.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 (CCPR2) register value is constantly compared against either the TMR1 register pair value, or the TMR3 register pair value. When a match occurs, the RC2/CCP1 (RC1/CCP2) pin can have one of the following actions: * * * * Driven high Driven low Toggle output (high to low or low to high) Remains unchanged Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode, if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation may not work. 14.4.3 SOFTWARE INTERRUPT MODE When Generate Software Interrupt is chosen, the CCP1 pin is not affected. Only a CCP Interrupt is generated (if enabled). 14.4.4 SPECIAL EVENT TRIGGER The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP2M3:CCP2M0). At the same time, interrupt flag bit CCP1IF (CCP2IF) is set. 14.4.1 CCP PIN CONFIGURATION In this mode, an internal hardware trigger is generated, which may be used to initiate an action. The special event trigger output of CCP1 resets the TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register for Timer1. The special trigger output of CCPx resets either the TMR1 or TMR3 register pair. Additionally, the CCP2 Special Event Trigger will start an A/D conversion if the A/D module is enabled. Note: The special event trigger from the CCP2 module will not set the Timer1 or Timer3 interrupt flag bits. The user must configure the CCPx pin as an output by clearing the appropriate TRISC bit. Note: Clearing the CCP1CON register will force the RC2/CCP1 compare output latch to the default low level. This is not the data latch. FIGURE 14-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will: Reset Timer1 or Timer3 (but not set Timer1 or Timer3 Interrupt Flag bit) Set bit GO/DONE, which starts an A/D conversion (CCP2 only) Special Event Trigger Set Flag bit CCP1IF CCPR1H CCPR1L Q RC2/CCP1 Pin TRISC<2> Output Enable S R Output Logic Comparator match CCP1M3:CCP1M0 Mode Select T3CCP2 0 1 TMR1H Special Event Trigger TMR1L TMR3H TMR3L Set Flag bit CCP2IF T3CCP1 T3CCP2 0 1 Q RC1/CCP2 Pin TRISC<1> Output Enable S R Output Logic Match Comparator CCPR2H CCPR2L CCP2M3:CCP2M0 Mode Select Note: I/O pins have diode protection to VDD and VSS. DS30475A-page 130 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 14-3: Name INTCON PIR1 PIE1 IPR1 TRISC TMR1L TMR1H T1CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON PIR2 PIE2 IPR2 TMR3L TMR3H T3CON REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1 AND TIMER3 Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF Bit 0 RBIF Value on POR, BOR Value on all other RESETS GIE/ GIEH PSPIF PSPIE PSPIP 0000 000x 0000 000u TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu PORTC Data Direction Register Holding register for the Least Significant Byte of the 16-bit TMR1 register Holding register for the Most Significant Byte of the 16-bit TMR1register RD16 -- Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- DC1B1 DC1B0 Capture/Compare/PWM register2 (LSB) Capture/Compare/PWM register2 (MSB) -- -- -- -- -- CMIF CMIE CMIP DC2B1 -- -- -- DC2B0 -- -- -- BCLIF BCLIE BCLIP LVDIF LVDIE LVDIP TMR3IF TMR3IE TMR3IP T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu CCP1M3 CCP1M2 CCP1M1 CCP1M0 --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M3 CCP2M2 CCP2M1 CCP2M0 --00 0000 --00 0000 CCP2IF -0-- 0000 -0-- 0000 CCP2IE -0-- 0000 -0-- 0000 CCP2IP -0-- 0000 -0-- 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu Holding register for the Least Significant Byte of the 16-bit TMR3 register Holding register for the Most Significant Byte of the 16-bit TMR3 register RD16 T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by Capture and Timer1. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 131 PIC18CXX8 14.5 PWM Mode 14.5.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: PWM period = [(PR2) + 1] * 4 * TOSC * (TMR2 prescale value) PWM frequency is defined as 1 / [PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: * TMR2 is cleared * The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) * The PWM duty cycle is latched from CCPR1L into CCPR1H Note: The Timer2 postscaler (see Section 12.0) is not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. PWM DUTY CYCLE Figure 14-3 shows a simplified block diagram of the CCP module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 14.5.3. FIGURE 14-3: SIMPLIFIED PWM BLOCK DIAGRAM Duty Cycle Registers CCPR1L (Master) CCP1CON<5:4> 14.5.2 CCPR1H (Slave) Q RC2/CCP1 TMR2 (Note 1) S TRISC<2> Clear Timer, CCP1 pin and latch D.C. Comparator R The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The following equation is used to calculate the PWM duty cycle in time: PWM duty cycle = (CCPR1L:CCP1CON<5:4>) * TOSC * (TMR2 prescale value) Comparator PR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock, or 2 bits of the prescaler, to create 10-bit time-base. CCPR1L and CCP1CON<5:4> can be written to at any time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 occurs (i.e., the period is complete). In PWM mode, CCPR1H is a read-only register. The CCPR1H register and a 2-bit internal latch are used to double buffer the PWM duty cycle. This double buffering is essential for glitchless PWM operation. When the CCPR1H and 2-bit latch match TMR2, concatenated with an internal 2-bit Q clock or 2 bits of the TMR2 prescaler, the CCP1 pin is cleared. Maximum PWM resolution (bits) for a given PWM frequency: FOSC log --------------- FPWM = -----------------------------bits log ( 2 ) A PWM output (Figure 14-4) has a time-base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 14-4: PWM OUTPUT Period Duty Cycle TMR2 = PR2 Note: TMR2 = Duty Cycle TMR2 = PR2 If the PWM duty cycle value is longer than the PWM period, the CCP1 pin will not be cleared. DS30475A-page 132 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 14.5.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. 3. 4. 5. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. TABLE 14-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 2.44 kHz 16 0xFF 10 9.76 kHz 4 0xFF 10 39.06 kHz 1 0xFF 10 156.3 kHz 1 0x3F 8 312.5 kHz 1 0x1F 7 416.6 kHz 1 0x17 5.5 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) TABLE 14-5: Name INTCON PIR1 PIE1 IPR1 TRISC TMR2 PR2 T2CON CCPR1L CCPR1H CCP1CON CCPR2L CCPR2H CCP2CON PIR2 PIE2 IPR2 Legend: Bit 7 REGISTERS ASSOCIATED WITH PWM AND TIMER2 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP Value on POR, BOR Value on all other RESETS GIE/ GIEH PSPIF PSPIE PSPIP 0000 000x 0000 000u 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 1111 1111 1111 1111 PORTC Data Direction Register Timer2 module's register Timer2 module's period register -- Capture/Compare/PWM register1 (LSB) Capture/Compare/PWM register1 (MSB) -- -- DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 Capture/Compare/PWM register2 (LSB) Capture/Compare/PWM register2 (MSB) -- -- -- -- -- CMIF CMIE CMIP DC2B1 -- -- -- DC2B0 -- -- -- CCP2M3 BCLIF BCLIE BCLIP CCP2M2 LVDIF LVDIE LVDIP CCP2M1 TMR3IF TMR3IE TMR3IP CCP2M0 CCP2IF CCP2IE CCP2IP TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu --00 0000 --00 0000 -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 -0-- 0000 x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by PWM and Timer2. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 133 PIC18CXX8 NOTES: DS30475A-page 134 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview 15.1 The Master Synchronous Serial Port (MSSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc. The MSSP module can operate in one of two modes: * Serial Peripheral InterfaceTM (SPI) * Inter-Integrated Circuit (I2C) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: * Master mode * Multi-master mode * Slave mode 2000 Microchip Technology Inc. Advanced Information DS30475A-page 135 PIC18CXX8 15.2 Control Registers The MSSP module has three associated registers. These include a status register and two control registers. Register 15-1 shows the MSSP Status Register (SSPSTAT), Register 15-2 shows the MSSP Control Register 1 (SSPCON1), and Register 15-3 shows the MSSP Control Register 2 (SSPCON2). REGISTER 15-1: SSPSTAT REGISTER R/W-0 SMP bit 7 R/W-0 CKE R-0 D/A R-0 P R-0 S R-0 R/W R-0 UA R-0 BF bit 0 bit 7 SMP: Sample bit SPI Master mode 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave mode SMP must be cleared when SPI is used in Slave mode In I2 C Master or Slave mode: 1= Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0= Slew rate control enabled for high speed mode (400 kHz) CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address P: STOP bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a STOP bit has been detected last (this bit is '0' on RESET) 0 = STOP bit was not detected last S: START bit (I2C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.) 1 = Indicates that a START bit has been detected last (this bit is '0' on RESET) 0 = START bit was not detected last R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next START bit, STOP bit, or not ACK bit. In I2 C Slave mode: 1 = Read 0 = Write In I2 C Master mode: 1 = Transmit is in progress 0 = Transmit is not in progress OR-ing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is in IDLE mode. bit 6 bit 5 bit 4 bit 3 bit 2 DS30475A-page 136 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 bit 1 UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated BF: Buffer Full Status bit Receive (SPI and I2 C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2 C mode only) 1 = Data Transmit in progress (does not include the ACK and STOP bits), SSPBUF is full 0 = Data Transmit complete (does not include the ACK and STOP bits), SSPBUF is empty Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 137 PIC18CXX8 REGISTER 15-2: SSPCON1 REGISTER R/W-0 WCOL bit 7 bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started 0 = No collision Slave mode: 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in Slave mode. In Slave mode, the user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. (Must be cleared in software.) 0 = No overflow In I2 C mode: 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don't care" in Transmit mode. (Must be cleared in software.) 0 = No overflow bit 5 SSPEN: Synchronous Serial Port Enable bit In both modes, when enabled, these pins must be properly configured as input or output. In SPI mode: 1 = Enables serial port and configures SCK, SDO, SDI, and SS as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2 C mode: 1 = Enables the serial port and configures the SDA and SCL pins as the source of the serial port pins 0 = Disables serial port and configures these pins as I/O port pins bit 4 CKP: Clock Polarity Select bit In SPI mode: 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2 C Slave mode: SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch). (Used to ensure data setup time.) In I2 C Master mode Unused in this mode R/W-0 SSPOV R/W-0 SSPEN R/W-0 CKP R/W-0 SSPM3 R/W-0 SSPM2 R/W-0 SSPM1 R/W-0 SSPM0 bit 0 DS30475A-page 138 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 bit 3 - 0 SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI Slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin. 0110 = I2C Slave mode, 7-bit address 0111 = I2C Slave mode, 10-bit address 1000 = I2C Master mode, clock = FOSC / (4 * (SSPADD+1) ) 1001 = Reserved 1010 = Reserved 1011 = I2C firmware controlled Master mode (Slave idle) 1100 = Reserved 1101 = Reserved 1110 = I2C Slave mode, 7-bit address with START and STOP bit interrupts enabled 1111 = I2C Slave mode, 10-bit address with START and STOP bit interrupts enabled Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 139 PIC18CXX8 REGISTER 15-3: SSPCON2 REGISTER R/W-0 GCEN bit 7 bit 7 GCEN: General Call Enable bit (In I2C Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled ACKSTAT: Acknowledge Status bit (In I2C Master mode only) In Master Transmit mode: 1 = Acknowledge was not received from slave 0 = Acknowledge was received from slave ACKDT: Acknowledge Data bit (In I2C Master mode only) In Master Receive mode: Value transmitted when the user initiates an Acknowledge sequence at the end of a receive 1 = Not Acknowledge 0 = Acknowledge ACKEN: Acknowledge Sequence Enable bit (In I2C Master mode only) In Master Receive mode: 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit. Automatically cleared by hardware. 0 = Acknowledge sequence idle RCEN: Receive Enable bit (In I2C Master mode only) 1 = Enables Receive mode for I2C 0 = Receive idle PEN: STOP Condition Enable bit (In I2C Master mode only) SCK release control 1 = Initiate STOP condition on SDA and SCL pins. Automatically cleared by hardware. 0 = STOP condition idle RSEN: Repeated START Condition Enabled bit (In I2C Master mode only) 1 = Initiate Repeated START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = Repeated START condition idle SEN: START Condition Enabled bit (In I2C Master mode only) 1 = Initiate START condition on SDA and SCL pins. Automatically cleared by hardware. 0 = START condition idle Note: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I2C module is not in the IDLE mode, this bit may not be set (no spooling) and the SSPBUF may not be written (or writes to the SSPBUF are disabled). R/W-0 ACKSTAT R/W-0 ACKDT R/W-0 ACKEN R/W-0 RCEN R/W-0 PEN R/W-0 RSEN R/W-0 SEN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS30475A-page 140 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received, simultaneously. All four modes of SPI are supported. To accomplish communication, typically three pins are used: * Serial Data Out (SDO) - RC5/SDO * Serial Data In (SDI) - RC4/SDI/SDA * Serial Clock (SCK) - RC3/SCK/SCL/LVOIN Additionally, a fourth pin may be used when in any Slave mode of operation: * Slave Select (SS) - RA5/SS/AN4 15.3.1 OPERATION SDI SDO bit0 FIGURE 15-1: MSSP BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPBUF reg Write SSPSR reg Shift Clock When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits SSPCON1<5:0> and SSPSTAT<7:6>. These control bits allow the following to be specified: Master mode (SCK is the clock output) Slave mode (SCK is the clock input) Clock polarity (Idle state of SCK) Data input sample phase (middle or end of data output time) * Clock edge (output data on rising/falling edge of SCK) * Clock rate (Master mode only) * Slave Select mode (Slave mode only) Figure 15-1 shows the block diagram of the MSSP module, when in SPI mode. * * * * SS SS Control Enable Edge Select 2 Clock Select SSPM3:SSPM0 SMP:CKE 4 TMR2 Output 2 2 Edge Select Prescaler TOSC 4, 16, 64 ( ) SCK Data to TX/RX in SSPSR TRIS bit Note: I/O pins have diode protection to VDD and VSS. The MSSP consists of a transmit/receive Shift Register (SSPSR) and a buffer register (SSPBUF). The SSPSR shifts the data in and out of the device, MSb first. The SSPBUF holds the data that was written to the SSPSR, until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPBUF register. Then the buffer full detect bit, BF (SSPSTAT register), and the interrupt flag bit, SSPIF (PIR registers), are set. This double buffering of the received data (SSPBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPBUF register during transmission/reception of data will be ignored, and the write collision detect bit, WCOL (SSPCON1 register), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPBUF register completed successfully. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 141 PIC18CXX8 When the application software is expecting to receive valid data, the SSPBUF should be read before the next byte of data to transfer is written to the SSPBUF. The buffer full (BF) bit (SSPSTAT register) indicates when SSPBUF has been loaded with the received data (transmission is complete). When the SSPBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP Interrupt is used to determine when the transmission/reception has completed. The SSPBUF must be read and/or written. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 15-1 shows the loading of the SSPBUF (SSPSR) for data transmission. The SSPSR is not directly readable or writable, and can only be accessed by addressing the SSPBUF register. Additionally, the MSSP status register (SSPSTAT register) indicates the various status conditions. 15.3.2 ENABLING SPI I/O To enable the serial port, SSP Enable bit, SSPEN (SSPCON1 register), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers, and then set the SSPEN bit. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed. That is: * SDI is automatically controlled by the SPI module * SDO must have TRISC<5> bit cleared * SCK (Master mode) must have TRISC<3> bit cleared * SCK (Slave mode) must have TRISC<3> bit set * SS must have TRISC<4> bit set Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. EXAMPLE 15-1: LOADING THE SSPBUF (SSPSR) REGISTER LOOP BTFSS SSPSTAT, BF GOTO LOOP MOVF SSPBUF, W MOVWF RXDATA MOVF TXDATA, W MOVWF SSPBUF ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSPBUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit DS30475A-page 142 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.3.3 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input). The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPBUF register as a normal received byte (interrupts and status bits appropriately set). This could be useful in receiver applications as a "line activity monitor" mode. The clock polarity is selected by appropriately programming the CKP bit (SSPCON1 register). This, then, would give waveforms for SPI communication as shown in Figure 15-2, Figure 15-4, and Figure 15-5, where the MSb is transmitted first. In Master mode, the SPI clock rate (bit rate) is user programmable to be one of the following: * * * * FOSC/4 (or TCY) FOSC/16 (or 4 * TCY) FOSC/64 (or 16 * TCY) Timer2 output/2 This allows a maximum data rate (at 40 MHz) of 10.00 Mbps. Figure 15-2 shows the waveforms for Master mode. When the CKE bit is set, the SDO data is valid before there is a clock edge on SCK. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown. FIGURE 15-2: SPI MODE WAVEFORM (MASTER MODE) Write to SSPBUF SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) SDO (CKE = 0) SDO (CKE = 1) SDI (SMP = 0) Input Sample (SMP = 0) SDI (SMP = 1) Input Sample (SMP = 1) SSPIF bit7 bit0 bit7 bit7 bit6 bit6 bit5 bit5 bit4 bit4 bit3 bit3 bit2 bit2 bit1 bit1 bit0 bit0 4 Clock Modes bit7 bit0 SSPSR to SSPBUF Next Q4 Cycle after Q2 2000 Microchip Technology Inc. Advanced Information DS30475A-page 143 PIC18CXX8 15.3.4 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin. This external clock must meet the minimum high and low times, as specified in the electrical specifications. While in SLEEP mode, the slave can transmit/receive data. When a byte is received, the device will wake-up from SLEEP. 15.3.5 SLAVE SELECT SYNCHRONIZATION the SDO pin is no longer driven, even if in the middle of a transmitted byte, and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. Note 1: When the SPI is in Slave mode with SS pin control enabled, (SSPCON<3:0> = 0100) the SPI module will reset if the SS pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SS pin control must be enabled. When the SPI module resets, the bit counter is forced to 0. This can be done by either forcing the SS pin to a high level, or clearing the SSPEN bit. To emulate two-wire communication, the SDO pin can be connected to the SDI pin. When the SPI needs to operate as a receiver, the SDO pin can be configured as an input. This disables transmissions from the SDO. The SDI can always be left as an input (SDI function), since it cannot create a bus conflict. The SS pin allows a Synchronous Slave mode. The SPI must be in Slave mode with SS pin control enabled (SSPCON1<3:0> = 04h). The pin must not be driven low for the SS pin to function as an input. The Data Latch must be high. When the SS pin is low, transmission and reception are enabled and the SDO pin is driven. When the SS pin goes high, FIGURE 15-3: SLAVE SYNCHRONIZATION WAVEFORM SS SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit7 bit6 bit7 bit0 SDI (SMP = 0) Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF bit0 bit7 bit7 Next Q4 Cycle after Q2 DS30475A-page 144 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 15-4: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF SSPSR to SSPBUF Next Q4 Cycle after Q2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 FIGURE 15-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Required SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) Input Sample (SMP = 0) SSPIF Next Q4 Cycle after Q2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit7 bit0 SSPSR to SSPBUF 2000 Microchip Technology Inc. Advanced Information DS30475A-page 145 PIC18CXX8 15.3.6 SLEEP OPERATION 15.3.8 BUS MODE COMPATIBILITY In Master mode, all module clocks are halted, and the transmission/reception will remain in that state until the device wakes from SLEEP. After the device returns to normal mode, the module will continue to transmit/receive data. In Slave mode, the SPI transmit/receive shift register operates asynchronously to the device. This allows the device to be placed in SLEEP mode, and data to be shifted into the SPI transmit/receive shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and, if enabled, will wake the device from SLEEP. 15.3.7 EFFECTS OF A RESET Table 15-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 15-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 There is also a SMP bit that controls when the data will be sampled. A RESET disables the MSSP module and terminates the current transfer. TABLE 15-2: Name INTCON PIR1 PIE1 IPR1 TRISC SSPBUF SSPCON TRISA SSPSTAT REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 Bit 6 PEIE/ GIEL ADIF ADIE ADIP Bit 5 TMR0IE RCIF RCIE RCIP Bit 4 INT0IE TXIF TXIE TXIP Bit 3 RBIE SSPIF SSPIE SSPIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF Bit 0 RBIF Value on POR, BOR Value on all other RESETS GIE/ GIEH PSPIF PSPIE PSPIP 0000 000x 0000 000u TMR2IF TMR1IF 0000 0000 0000 0000 TMR2IE TMR1IE 0000 0000 0000 0000 TMR2IP TMR1IP 0000 0000 0000 0000 1111 1111 1111 1111 xxxx xxxx uuuu uuuu PORTC Data Direction Register Synchronous Serial Port Receive Buffer/Transmit Register WCOL -- SMP SSPOV SSPEN CKP SSPM3 (1) SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 --11 1111 --11 1111 PORTA Data Direction Register CKE D/A P S R/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used by the MSSP in SPI mode. Note 1: Bit 6 of PORTA, LATA and TRISA are enabled in ECIO and RCIO oscillator modes only. In all other oscillator modes, they are disabled and read `0'. DS30475A-page 146 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4 MSSP I2 C Operation The MSSP module in I 2C mode, fully implements all master and slave functions (including general call support) and provides interrupts on START and STOP bits in hardware to determine a free bus (Multi-master mode). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RC3/SCK/SCL pin, which is the clock (SCL), and the RC4/SDI/SDA pin, which is the data (SDA). The user must configure these pins as inputs or outputs through the TRISC<4:3> bits. The MSSP module functions are enabled by setting MSSP Enable bit SSPEN (SSPCON1 register). The SSPCON1 register allows control of the I 2C operation. The SSPM3:SSPM0 mode selection bits (SSPCON1 register) allow one of the following I 2C modes to be selected: * * * * I2C Master mode, clock = OSC/4 (SSPADD +1) I 2C Slave mode (7-bit address) I 2C Slave mode (10-bit address) I 2C Slave mode (7-bit address), with START and STOP bit interrupts enabled * I 2C Slave mode (10-bit address), with START and STOP bit interrupts enabled * I 2C Firmware controlled master operation, slave is idle FIGURE 15-6: MSSP BLOCK DIAGRAM (I2C MODE) Internal Data Bus Read SSPBUF reg Shift Clock SSPSR reg RC4/ SDI/ SDA MSb LSb Write Selection of any I 2C mode with the SSPEN bit set, forces the SCL and SDA pins to be open drain, provided these pins are programmed to inputs by setting the appropriate TRISC bits. 15.4.1 SLAVE MODE In Slave mode, the SCL and SDA pins must be configured as inputs (TRISC<4:3> set). The MSSP module will override the input state with the output data when required (slave-transmitter). When an address is matched, or the data transfer after an address match is received, the hardware automatically will generate the acknowledge (ACK) pulse and load the SSPBUF register with the received value currently in the SSPSR register. If either or both of the following conditions are true, the MSSP module will not give this ACK pulse: RC3/SCK/SCL Match Detect Addr Match a) b) SSPADD reg START and STOP bit detect Set, RESET S, P bits (SSPSTAT reg) The buffer full bit BF (SSPCON1 register) was set before the transfer was received. The overflow bit SSPOV (SSPCON1 register) was set before the transfer was received. In this event, the SSPSR register value is not loaded into the SSPBUF, but bit SSPIF (PIR registers) is set. The BF bit is cleared by reading the SSPBUF register, while bit SSPOV is cleared through software. The SCL clock input must have a minimum high and low for proper operation. The high and low times of the I2C specification, as well as the requirement of the MSSP module, is shown in timing parameter #100 and parameter #101. Note: I/O pins have diode protection to VDD and VSS. The MSSP module has these six registers for I2C operation: * * * * * MSSP Control Register1 (SSPCON1) MSSP Control Register2 (SSPCON2) MSSP Status Register (SSPSTAT) Serial Receive/Transmit Buffer (SSPBUF) MSSP Shift Register (SSPSR) - Not directly accessible * MSSP Address Register (SSPADD) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 147 PIC18CXX8 15.4.1.1 Addressing Once the MSSP module has been enabled, it waits for a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse. If the addresses match, and the BF and SSPOV bits are clear, the following events occur: a) b) c) d) The SSPSR register value is loaded into the SSPBUF register. The buffer full bit BF is set. An ACK pulse is generated. MSSP interrupt flag bit SSPIF (PIR registers) is set on the falling edge of the ninth SCL pulse (interrupt is generated, if enabled). The sequence of events for 10-bit addressing is as follows, with steps 7- 9 for slave-transmitter: 1. 2. Receive first (high) byte of address (the SSPIF, BF and UA bits (SSPSTAT register) are set). Update the SSPADD register with second (low) byte of address (clears bit UA and releases the SCL line). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive second (low) byte of address (bits SSPIF, BF, and UA are set). Update the SSPADD register with the first (high) byte of address. If match releases SCL line, this will clear bit UA. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. Receive repeated START condition. Receive first (high) byte of address (bits SSPIF and BF are set). Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. 3. 4. 5. 6. 7. 8. 9. In 10-bit address mode, two address bytes need to be received by the slave. The five Most Significant bits (MSb) of the first address byte specify if this is a 10-bit address. The R/W bit (SSPSTAT register) must specify a write so the slave device will receive the second address byte. For a 10-bit address, the first byte would equal `1111 0 A9 A8 0', where A9 and A8 are the two MSb's of the address. DS30475A-page 148 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.1.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register. When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT register) is set or bit SSPOV (SSPCON1 register) is set. An MSSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR registers) must be cleared in software. The SSPSTAT register is used to determine the status of the byte. 15.4.1.3 Transmission ter. Then pin RC3/SCK/SCL should be enabled by setting bit CKP (SSPCON1 register). The master must monitor the SCL pin prior to asserting another clock pulse. The slave devices may be holding off the master by stretching the clock. The eight data bits are shifted out on the falling edge of the SCL input. This ensures that the SDA signal is valid during the SCL high time (Figure 15-8). An MSSP interrupt is generated for each data transfer byte. The SSPIF bit must be cleared in software and the SSPSTAT register is used to determine the status of the byte. The SSPIF bit is set on the falling edge of the ninth clock pulse. As a slave-transmitter, the ACK pulse from the master-receiver is latched on the rising edge of the ninth SCL input pulse. If the SDA line is high (not ACK), then the data transfer is complete. When the ACK is latched by the slave, the slave logic is reset (resets SSPSTAT register) and the slave monitors for another occurrence of the START bit. If the SDA line was low (ACK), the transmit data must be loaded into the SSPBUF register, which also loads the SSPSR register. Pin RC3/SCK/SCL should be enabled by setting bit CKP. When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPSTAT register is set. The received address is loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit and pin RC3/SCK/SCL is held low. The transmit data must be loaded into the SSPBUF register, which also loads the SSPSR regis- FIGURE 15-7: I 2C SLAVE MODE WAVEFORMS FOR RECEPTION (7-BIT ADDRESS) SDA Receiving Address R/W=0 Receiving Data Receiving Data Not ACK ACK ACK A7 A6 A5 A4 A3 A2 A1 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 S 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 SCL SSPIF 9 1 2 3 4 5 6 7 8 9 P Bus Master Terminates Transfer Cleared in software SSPBUF register is read BF SSPOV Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. FIGURE 15-8: I 2C SLAVE MODE WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS) Receiving Address SDA R/W = 1 Transmitting Data R/W = 0 Not ACK A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0 SCL S 1 2 Data in Sampled 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 9 P SSPIF BF Cleared in software SSPBUF is written in software CKP Set bit after writing to SSPBUF (the SSPBUF must be written to before the CKP bit can be set) From SSP interrupt service routine 2000 Microchip Technology Inc. Advanced Information DS30475A-page 149 PIC18CXX8 15.4.2 GENERAL CALL ADDRESS SUPPORT I2 C bus is such that The addressing procedure for the the first byte after the START condition usually determines which device will be the slave addressed by the master. The exception is the general call address, which can address all devices. When this address is used, all devices should, in theory, respond with an acknowledge. The general call address is one of eight addresses reserved for specific purposes by the I2C protocol. It consists of all 0's with R/W = 0. The general call address is recognized (enabled) when the General Call Enable (GCEN) bit is set (SSPCON2 register). Following a START bit detect, eight bits are shifted into the SSPSR and the address is compared against the SSPADD. It is also compared to the general call address and fixed in hardware. If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF bit is set (eighth bit), and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. When the interrupt is serviced, the source for the interrupt can be checked by reading the contents of the SSPBUF. The value can be used to determine if the address was device specific or a general call address. In 10-bit mode, the SSPADD is required to be updated for the second half of the address to match, and the UA bit is set (SSPSTAT register). If the general call address is sampled when the GCEN bit is set, and while the slave is configured in 10-bit address mode; then, the second half of the address is not necessary. The UA bit will not be set, and the slave will begin receiving data after the Acknowledge (Figure 15-9). FIGURE 15-9: SLAVE MODE GENERAL CALL ADDRESS SEQUENCE (7 OR 10-BIT ADDRESS) Address is compared to General Call Address after ACK, set interrupt R/W = 0 ACK D7 Receiving data D6 D5 D4 D3 D2 D1 D0 ACK SDA SCL S SSPIF BF 1 General Call Address 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 Cleared in software SSPBUF is read SSPOV '0' GCEN '1' DS30475A-page 150 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.3 MASTER MODE 15.4.4 I2C MASTER MODE SUPPORT Master mode of operation is supported by interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit is set, or the bus is idle, with both the S and P bits clear. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. The following events will cause SSP Interrupt Flag bit, SSPIF, to be set (SSP Interrupt if enabled): * * * * * START condition STOP condition Data transfer byte transmitted/received Acknowledge Transmit Repeated START condition Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. Once Master mode is enabled, the user has the following six options: 1. 2. 3. 4. 5. 6. Assert a START condition on SDA and SCL. Assert a Repeated START condition on SDA and SCL. Write to the SSPBUF register initiating transmission of data/address. Generate a STOP condition on SDA and SCL. Configure the I2C port to receive data. Generate an Acknowledge condition at the end of a received byte of data. The MSSP module, when configured in I2C Master mode, does not allow queueing of events. For instance, the user is not allowed to initiate a START condition and immediately write the SSPBUF register to imitate transmission before the START condition is complete. In this case, the SSPBUF will not be written to and the WCOL bit will be set, indicating that a write to the SSPBUF did not occur. Note: FIGURE 15-10: MSSP BLOCK DIAGRAM (I2C MASTER MODE) Internal Data Bus SSPM3:SSPM0 SSPADD<6:0> Read SSPBUF SDA SDA In SSPSR Receive Enable MSb Write Baud Rate Generator Clock arbitrate/WCOL Detect (hold off clock source) DS30475A-page 151 Shift Clock LSb SCL SCL In Bus Collision START bit Detect STOP bit Detect Write Collision Detect Clock Arbitration State Counter for End of XMIT/RCV Set/Reset, S, P, WCOL (SSPSTAT) Set SSPIF, BCLIF Reset ACKSTAT, PEN (SSPCON2) Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information Clock Cntl START bit, STOP bit, Acknowledge Generate PIC18CXX8 15.4.4.1 I2C Master Mode Operation A typical transmit sequence would go as follows: a) The user generates a START condition by setting the START Enable (SEN) bit (SSPCON2 register). SSPIF is set. The MSSP module will wait the required start time before any other operation takes place. The user loads the SSPBUF with the address to transmit. Address is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit (SSPCON2 register). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user loads the SSPBUF with eight bits of data. Data is shifted out the SDA pin until all eight bits are transmitted. The MSSP module shifts in the ACK bit from the slave device and writes its value into the ACKSTAT bit (SSPCON2 register). The MSSP module generates an interrupt at the end of the ninth clock cycle by setting the SSPIF bit. The user generates a STOP condition by setting the STOP Enable bit PEN (SSPCON2 register). Interrupt is generated once the STOP condition is complete. The master device generates all of the serial clock pulses and the START and STOP conditions. A transfer is ended with a STOP condition or with a Repeated START condition. Since the Repeated START condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock. The first byte transmitted contains the slave address of the receiving device (7 bits) and the Read/Write (R/W) bit. In this case, the R/W bit will be logic '0'. Serial data is transmitted eight bits at a time. After each byte is transmitted, an Acknowledge bit is received. START and STOP conditions are output to indicate the beginning and the end of a serial transfer. In Master Receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the R/W bit. In this case, the R/W bit will be logic '1'. Thus, the first byte transmitted is a 7-bit slave address followed by a '1' to indicate receive bit. Serial data is received via SDA, while SCL outputs the serial clock. Serial data is received eight bits at a time. After each byte is received, an Acknowledge bit is transmitted. START and STOP conditions indicate the beginning and end of transmission. The baud rate generator used for the SPI mode operation is now used to set the SCL clock frequency for either 100 kHz, 400 kHz, or 1 MHz I2C operation. The baud rate generator reload value is contained in the lower 7 bits of the SSPADD register. The baud rate generator will automatically begin counting on a write to the SSPBUF. Once the given operation is complete (i.e., transmission of the last data bit is followed by ACK), the internal clock will automatically stop counting and the SCL pin will remain in its last state. b) c) d) e) f) g) h) i) j) k) l) DS30475A-page 152 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.5 2 BAUD RATE GENERATOR In I C Master mode, the reload value for the BRG is located in the lower 7 bits of the SSPADD register (Figure 15-11). When the BRG is loaded with this value, the BRG counts down to 0 and stops until another reload has taken place. The BRG count is dec- remented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically. If Clock Arbitration is taking place, for instance, the BRG will be reloaded when the SCL pin is sampled high (Figure 15-12). FIGURE 15-11: BAUD RATE GENERATOR BLOCK DIAGRAM SSPM3:SSPM0 SSPADD<6:0> SSPM3:SSPM0 SCL Reload Control CLKOUT Reload BRG Down Counter Fosc/4 FIGURE 15-12: BAUD RATE GENERATOR TIMING WITH CLOCK ARBITRATION SDA DX DX-1 SCL allowed to transition high SCL de-asserted but slave holds SCL low (clock arbitration) SCL BRG decrements on Q2 and Q4 cycles BRG value 03h 02h 01h 00h (hold off) 03h 02h SCL is sampled high, reload takes place and BRG starts its count. BRG reload 2000 Microchip Technology Inc. Advanced Information DS30475A-page 153 PIC18CXX8 15.4.6 I2C MASTER MODE START CONDITION TIMING 15.4.6.1 WCOL Status Flag If the user writes the SSPBUF when a START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing to the lower 5 bits of SSPCON2 is disabled until the START condition is complete. To initiate a START condition, the user sets the START Condition Enable (SEN) bit (SSPCON2 register). If the SDA and SCL pins are sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the baud rate generator times out (TBRG), the SDA pin is driven low. The action of the SDA being driven low, while SCL is high, is the START condition, and causes the S bit (SSPSTAT register) to be set. Following this, the baud rate generator is reloaded with the contents of SSPADD<6:0> and resumes its count. When the baud rate generator times out (TBRG), the SEN bit (SSPCON2 register) will be automatically cleared by hardware, the baud rate generator is suspended leaving the SDA line held low and the START condition is complete. Note: If at the beginning of the START condition, the SDA and SCL pins are already sampled low, or if during the START condition the SCL line is sampled low before the SDA line is driven low, a bus collision occurs, the Bus Collision Interrupt Flag BCLIF is set, the START condition is aborted, and the I2C module is reset into its IDLE state. FIGURE 15-13: FIRST START BIT TIMING Set S bit (SSPSTAT) SDA = 1, SCL = 1 At completion of START bit, Hardware clears SEN bit and sets SSPIF bit TBRG Write to SSPBUF occurs here 1st Bit SDA TBRG 2nd Bit Write to SEN bit occurs here TBRG SCL S TBRG DS30475A-page 154 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.7 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode, or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode). 15.4.7.1 WCOL Status Flag A Repeated START condition occurs when the RSEN bit (SSPCON2 register) is programmed high and the I2C logic module is in the IDLE state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the baud rate generator is loaded with the contents of SSPADD<5:0> and begins counting. The SDA pin is released (brought high) for one baud rate generator count (TBRG). When the baud rate generator times out, if SDA is sampled high, the SCL pin will be de-asserted (brought high). When SCL is sampled high, the baud rate generator is re-loaded with the contents of SSPADD<6:0> and begins counting. SDA and SCL must be sampled high for one TBRG. This action is then followed by assertion of the SDA pin (SDA = 0) for one TBRG, while SCL is high. Following this, the RSEN bit (SSPCON2 register) will be automatically cleared and the baud rate generator will not be reloaded, leaving the SDA pin held low. As soon as a START condition is detected on the SDA and SCL pins, the S bit (SSPSTAT register) will be set. The SSPIF bit will not be set until the baud rate generator has timed-out. Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. 2: A bus collision during the Repeated START condition occurs if: * SDA is sampled low when SCL goes from low to high. * SCL goes low before SDA is asserted low. This may indicate that another master is attempting to transmit a data "1". If the user writes the SSPBUF when a Repeated START sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). Note: Because queueing of events is not allowed, writing of the lower 5 bits of SSPCON2 is disabled until the Repeated START condition is complete. FIGURE 15-14: REPEAT START CONDITION WAVEFORM Set S (SSPSTAT<3>) Write to SSPCON2 occurs here. SDA = 1, SCL(no change) SDA = 1, SCL = 1 At completion of START bit, hardware clear RSEN bit and set SSPIF TBRG 1st Bit SDA Falling edge of ninth clock End of Xmit Write to SSPBUF occurs here. TBRG TBRG TBRG TBRG Sr = Repeated START SCL 2000 Microchip Technology Inc. Advanced Information DS30475A-page 155 PIC18CXX8 15.4.8 I2C MASTER MODE TRANSMISSION 15.4.8.2 WCOL Status Flag Transmission of a data byte, a 7-bit address, or the other half of a 10-bit address, is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full bit, BF, and allow the baud rate generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter 106). SCL is held low for one baud rate generator roll over count (TBRG). Data should be valid before SCL is released high (see data setup time specification parameter 107). When the SCL pin is released high, it is held that way for TBRG. The data on the SDA pin must remain stable for that duration and some hold time after the next falling edge of SCL. After the eighth bit is shifted out (the falling edge of the eighth clock), the BF bit is cleared and the master releases SDA, allowing the slave device being addressed to respond with an ACK bit during the ninth bit time if an address match occurs, or if data was received properly. The status of ACK is written into the ACKDT bit on the falling edge of the ninth clock. If the master receives an acknowledge, the Acknowledge Status bit, ACKSTAT, is cleared. If not, the bit is set. After the ninth clock, the SSPIF bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the SSPBUF, leaving SCL low and SDA unchanged (Figure 15-15). After the write to the SSPBUF, each bit of address will be shifted out on the falling edge of SCL, until all seven address bits and the R/W bit, are completed. On the falling edge of the eighth clock, the master will de-assert the SDA pin, allowing the slave to respond with an acknowledge. On the falling edge of the ninth clock, the master will sample the SDA pin to see if the address was recognized by a slave. The status of the ACK bit is loaded into the ACKSTAT status bit (SSPCON2 register). Following the falling edge of the ninth clock transmission of the address, the SSPIF is set, the BF bit is cleared and the baud rate generator is turned off, until another write to the SSPBUF takes place, holding SCL low and allowing SDA to float. 15.4.8.1 BF Status Flag If the user writes the SSPBUF when a transmit is already in progress (i.e., SSPSR is still shifting out a data byte), the WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). WCOL must be cleared in software. 15.4.8.3 ACKSTAT Status Flag In Transmit mode, the ACKSTAT bit (SSPCON2 register) is cleared when the slave has sent an acknowledge (ACK = 0), and is set when the slave does not acknowledge (ACK = 1). A slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 15.4.9 I2C MASTER MODE RECEPTION Master mode reception is enabled by programming the Receive Enable bit, RCEN (SSPCON2 register). Note: The MSSP module must be in an IDLE state before the RCEN bit is set, or the RCEN bit will be disregarded. The baud rate generator begins counting, and on each rollover, the state of the SCL pin changes (high to low/low to high) and data is shifted into the SSPSR. After the falling edge of the eighth clock, the RCEN bit is automatically cleared, the contents of the SSPSR are loaded into the SSPBUF, the BF bit is set, the SSPIF flag bit is set and the baud rate generator is suspended from counting, holding SCL low. The MSSP is now in IDLE state, awaiting the next command. When the buffer is read by the CPU, the BF bit is automatically cleared. The user can then send an Acknowledge bit at the end of reception, by setting the Acknowledge Sequence Enable bit ACKEN (SSPCON2 register). 15.4.9.1 BF Status Flag In receive operation, the BF bit is set when an address or data byte is loaded into SSPBUF from SSPSR. It is cleared when the SSPBUF register is read. 15.4.9.2 SSPOV Status Flag In Transmit mode, the BF bit (SSPSTAT register) is set when the CPU writes to SSPBUF, and is cleared when all eight bits are shifted out. In receive operation, the SSPOV bit is set when eight bits are received into the SSPSR and the BF bit is already set from a previous reception. 15.4.9.3 WCOL Status Flag If the user writes the SSPBUF when a receive is already in progress (i.e., SSPSR is still shifting in a data byte), the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). DS30475A-page 156 Advanced Information 2000 Microchip Technology Inc. Write SSPCON2<0> SEN = 1 START condition begins From slave, clear ACKSTAT bit SSPCON2<6> R/W = 0 A1 ACK = 0 D7 D6 D5 D4 D3 D2 Transmitting Data or Second Half of 10-bit Address D1 D0 SEN = 0 Transmit Address to Slave SDA A7 SSPBUF written with 7-bit address and R/W start transmit SCL S 1 2 3 4 5 6 7 8 9 1 SCL held low while CPU responds to SSPIF 2 3 4 5 6 7 8 A6 A5 A4 A3 A2 2000 Microchip Technology Inc. ACKSTAT in SSPCON2 = 1 ACK 9 P SSPIF Cleared in software Cleared in software service routine From SSP interrupt Cleared in software BF SSPBUF written SEN After START condition, SEN cleared by hardware. SSPBUF is written in software PEN R/W FIGURE 15-15: I 2C MASTER MODE WAVEFORM (TRANSMISSION, 7 OR 10-BIT ADDRESS) Advanced Information PIC18CXX8 DS30475A-page 157 PIC18CXX8 DS30475A-page 158 Write to SSPCON2<4> to start acknowledge sequence SDA = ACKDT (SSPCON2<5>) = 0 Master configured as a receiver by programming SSPCON2<3>, (RCEN = 1) ACK from Slave R/W = 1 Receiving Data from Slave ACK Receiving Data from Slave RCEN cleared automatically ACK RCEN = 1 start next receive RCEN cleared automatically ACK from Master SDA = ACKDT = 0 Set ACKEN start acknowledge sequence SDA = ACKDT = 1 PEN bit = 1 written here Write to SSPCON2<0> (SEN = 1) Begin START Condition SEN = 0 Write to SSPBUF occurs here Start XMIT Transmit Address to Slave SDA D0 A7 A1 D7 D6 D5 D4 D3 D2 D1 D7 D6 D5 D4 D3 D2 D1 A6 A5 A4 A3 A2 D0 ACK ACK is not sent Bus Master terminates transfer 6 7 8 9 P Set SSPIF at end of receive Set SSPIF interrupt at end of acknowledge sequence SCL S Set SSPIF interrupt at end of receive 1 5 1 2 3 4 5 1 2 3 4 5 2 3 4 8 6 7 8 9 6 7 9 Data shifted in on falling edge of CLK SSPIF Cleared in software Cleared in software Set SSPIF interrupt at end of acknowledge sequence Cleared in software Cleared in software SDA = 0, SCL = 1 while CPU responds to SSPIF Cleared in software Set P bit (SSPSTAT<4>) and SSPIF FIGURE 15-16: I 2C MASTER MODE WAVEFORM (RECEPTION, 7-BIT ADDRESS) Advanced Information Last bit is shifted into SSPSR and contents are unloaded into SSPBUF BF SSPOV SSPOV is set because SSPBUF is still full 2000 Microchip Technology Inc. ACKEN PIC18CXX8 15.4.10 ACKNOWLEDGE SEQUENCE TIMING An acknowledge sequence is enabled by setting the Acknowledge Sequence Enable bit ACKEN (SSPCON2 register). When this bit is set, the SCL pin is pulled low and the contents of the Acknowledge Data bit (ACKDT) is presented on the SDA pin. If the user wishes to generate an acknowledge, then the ACKDT bit should be cleared. If not, the user should set the ACKDT bit before starting an acknowledge sequence. The baud rate generator then counts for one rollover period (TBRG) and the SCL pin is de-asserted (pulled high). When the SCL pin is sampled high (clock arbitration), the baud rate generator counts for TBRG. The SCL pin is then pulled low. Following this, the ACKEN bit is automatically cleared, the baud rate generator is turned off and the MSSP module then goes into IDLE mode (Figure 15-17). 15.4.10.1 WCOL Status Flag If the user writes the SSPBUF when an acknowledge sequence is in progress, then WCOL is set and the contents of the buffer are unchanged (the write doesn't occur). 15.4.11 STOP CONDITION TIMING A STOP bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2 register). At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the baud rate generator is reloaded and counts down to 0. When the baud rate generator times out, the SCL pin will be brought high, and one TBRG (baud rate generator rollover count) later, the SDA pin will be de-asserted. When the SDA pin is sampled high while SCL is high, the P bit (SSPSTAT register) is set. A TBRG later, the PEN bit is cleared and the SSPIF bit is set (Figure 15-18). 15.4.11.1 WCOL Status Flag If the user writes the SSPBUF when a STOP sequence is in progress, then the WCOL bit is set and the contents of the buffer are unchanged (the write doesn't occur). FIGURE 15-17: ACKNOWLEDGE SEQUENCE WAVEFORM Acknowledge sequence starts here, Write to SSPCON2 ACKEN = 1, ACKDT = 0 TBRG SDA D0 ACK TBRG ACKEN automatically cleared SCL 8 9 SSPIF Set SSPIF at the end of receive Cleared in software Cleared in software Set SSPIF at the end of Acknowledge sequence Note: TBRG = one baud rate generator period. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 159 PIC18CXX8 FIGURE 15-18: STOP CONDITION RECEIVE OR TRANSMIT MODE Write to SSPCON2 Set PEN Falling edge of 9th clock TBRG SCL SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT) is set PEN bit (SSPCON2) is cleared by hardware and the SSPIF bit is set SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to set up STOP condition. Note: TBRG = one baud rate generator period. DS30475A-page 160 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.12 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated START/STOP condition, de-asserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the baud rate generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the baud rate generator is reloaded with the contents of SSPADD<6:0> and begins counting. This ensures that the SCL high time will always be at least one BRG rollover count, in the event that the clock is held low by an external device (Figure 15-19). 15.4.13 SLEEP OPERATION While in SLEEP mode, the I2C module can receive addresses or data, and when an address match or complete byte transfer occurs, wake the processor from SLEEP (if the MSSP interrupt is enabled). 15.4.14 EFFECT OF A RESET A RESET disables the MSSP module and terminates the current transfer. FIGURE 15-19: CLOCK ARBITRATION TIMING IN MASTER TRANSMIT MODE BRG overflow, Release SCL, If SCL = 1 Load BRG with SSPADD<6:0>, and start count to measure high time interval. BRG overflow occurs, Release SCL, Slave device holds SCL low. SCL = 1 BRG starts counting clock high interval. SCL SCL line sampled once every machine cycle (TOSC 4). Hold off BRG until SCL is sampled high. SDA TBRG TBRG TBRG 2000 Microchip Technology Inc. Advanced Information DS30475A-page 161 PIC18CXX8 15.4.15 MULTI-MASTER MODE In Multi-master mode, the interrupt generation on the detection of the START and STOP conditions allows the determination of when the bus is free. The STOP (P) and START (S) bits are cleared from a RESET, or when the MSSP module is disabled. Control of the I 2C bus may be taken when the P bit (SSPSTAT register) is set, or the bus is idle with both the S and P bits clear. When the bus is busy, enabling the SSP Interrupt will generate the interrupt when the STOP condition occurs. In Multi-master operation, the SDA line must be monitored for arbitration, to see if the signal level is the expected output level. This check is performed in hardware, with the result placed in the BCLIF bit. Arbitration can be lost in the following states: * * * * * Address transfer Data transfer A START condition A Repeated START condition An Acknowledge condition 15.4.16 MULTI -MASTER COMMUNICATION, BUS COLLISION, AND BUS ARBITRATION Multi-master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDA pin, arbitration takes place when the master outputs a '1' on SDA, by letting SDA float high and another master asserts a '0'. When the SCL pin floats high, data should be stable. If the expected data on SDA is a '1' and the data sampled on the SDA pin = '0', then a bus collision has taken place. The master will set the Bus Collision Interrupt Flag (BCLIF) and reset the I2C port to its IDLE state. (Figure 15-20). If a transmit was in progress when the bus collision occurred, the transmission is halted, the BF bit is cleared, the SDA and SCL lines are de-asserted, and the SSPBUF can be written to. When the user services the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. If a START, Repeated START, STOP, or Acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the SDA and SCL lines are de-asserted, and the respective control bits in the SSPCON2 register are cleared. When the user services the bus collision interrupt service routine, and if the I2C bus is free, the user can resume communication by asserting a START condition. The master will continue to monitor the SDA and SCL pins. If a STOP condition occurs, the SSPIF bit will be set. A write to the SSPBUF will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. In Multi-master mode, the interrupt generation on the detection of START and STOP conditions allows the determination of when the bus is free. Control of the I2C bus can be taken when the P bit is set in the SSPSTAT register, or the bus is idle and the S and P bits are cleared. FIGURE 15-20: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master SDA SCL BCLIF Set bus collision interrupt (BCLIF) Sample SDA. While SCL is high data doesn't match what is driven by the master. Bus collision has occurred. DS30475A-page 162 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.16.1 Bus Collision During a START Condition During a START condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the START condition (Figure 15-21). SCL is sampled low before SDA is asserted low (Figure 15-22). The START condition begins with the SDA and SCL pins de-asserted. When the SDA pin is sampled high, the baud rate generator is loaded from SSPADD<6:0> and counts down to 0. If the SCL pin is sampled low while SDA is high, a bus collision occurs, because it is assumed that another master is attempting to drive a data '1' during the START condition. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 15-23). If, however, a '1' is sampled on the SDA pin, the SDA pin is asserted low at the end of the BRG count. The baud rate generator is then reloaded and counts down to 0, and during this time, if the SCL pin is sampled as '0', a bus collision does not occur. At the end of the BRG count, the SCL pin is asserted low. Note: The reason that bus collision is not a factor during a START condition is that no two bus masters can assert a START condition at the exact same time. Therefore, one master will always assert SDA before the other. This condition does not cause a bus collision, because the two masters must be allowed to arbitrate the first address following the START condition. If the address is the same, arbitration must be allowed to continue into the data portion, Repeated START or STOP conditions. During a START condition, both the SDA and the SCL pins are monitored. If: the SDA pin is already low or the SCL pin is already low, then: the START condition is aborted, and the BCLIF flag is set, and the MSSP module is reset to its IDLE state (Figure 15-21). FIGURE 15-21: BUS COLLISION DURING START CONDITION (SDA ONLY) SDA goes low before the SEN bit is set. . Set BCLIF, S bit and SSPIF set because SDA = 0, SCL = 1. SDA SCL Set SEN, enable START condition if SDA = 1, SCL = 1. SEN SDA sampled low before START condition. Set BCLIF. S bit and SSPIF set because SDA = 0, SCL = 1. SSPIF and BCLIF are cleared in software. S SEN cleared automatically because of bus collision. SSP module reset into IDLE state. BCLIF SSPIF SSPIF and BCLIF are cleared in software. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 163 PIC18CXX8 FIGURE 15-22: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable START sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, Bus collision occurs, set BCLIF SCL = 0 before BRG time-out, Bus collision occurs, set BCLIF SCL SEN BCLIF Interrupt cleared in software S SSPIF '0' '0' '0' '0' FIGURE 15-23: BRG RESET DUE TO SDA ARBITRATION DURING START CONDITION SDA = 0, SCL = 1 Set S Less than TBRG TBRG Set SSPIF SDA SDA pulled low by other master Reset BRG and assert SDA SCL SEN BCLIF S SCL pulled low after BRG Time-out Set SEN, enable START sequence if SDA = 1, SCL = 1 '0' S SSPIF SDA = 0, SCL = 1 Set SSPIF Interrupts cleared in software DS30475A-page 164 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 15.4.16.2 Bus Collision During a Repeated START Condition During a Repeated START condition, a bus collision occurs if: a) b) A low level is sampled on SDA when SCL goes from low level to high level. SCL goes low before SDA is asserted low, indicating that another master is attempting to transmit a data '1'. reloaded and begins counting. If SDA goes from high to low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time. If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data '1' during the Repeated START condition (Figure 15-25). If at the end of the BRG time-out both SCL and SDA are still high, the SDA pin is driven low and the BRG is reloaded and begins counting. At the end of the count, regardless of the status of the SCL pin, the SCL pin is driven low and the Repeated START condition is complete. When the user de-asserts SDA and the pin is allowed to float high, the BRG is loaded with SSPADD<6:0> and counts down to 0. The SCL pin is then de-asserted, and when sampled high, the SDA pin is sampled. If SDA is low, a bus collision has occurred (i.e, another master is attempting to transmit a data '0', see Figure 15-24). If SDA is sampled high, the BRG is FIGURE 15-24: BUS COLLISION DURING A REPEATED START CONDITION (CASE 1) SDA SCL Sample SDA when SCL goes high. If SDA = 0, set BCLIF and release SDA and SCL. RSEN BCLIF Cleared in software. '0' '0' S SSPIF FIGURE 15-25: BUS COLLISION DURING REPEATED START CONDITION (CASE 2) TBRG SDA SCL BCLIF SCL goes low before SDA. Set BCLIF, release SDA and SCL. Interrupt cleared in software. RSEN S SSPIF '0' TBRG 2000 Microchip Technology Inc. Advanced Information DS30475A-page 165 PIC18CXX8 15.4.16.3 Bus Collision During a STOP Condition Bus collision occurs during a STOP condition if: a) After the SDA pin has been de-asserted and allowed to float high, SDA is sampled low after the BRG has timed out. After the SCL pin is de-asserted, SCL is sampled low before SDA goes high. The STOP condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the baud rate generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data '0' (Figure 15-26). If the SCL pin is sampled low before SDA is allowed to float high, a bus collision occurs. This is another case of another master attempting to drive a data '0' (Figure 15-27). b) FIGURE 15-26: BUS COLLISION DURING A STOP CONDITION (CASE 1) TBRG SDA SDA asserted low TBRG TBRG SDA sampled low after TBRG, set BCLIF SCL PEN BCLIF P SSPIF '0' '0' FIGURE 15-27: BUS COLLISION DURING A STOP CONDITION (CASE 2) TBRG SDA Assert SDA SCL goes low before SDA goes high, set BCLIF TBRG TBRG SCL PEN BCLIF P SSPIF '0' '0' DS30475A-page 166 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: * Asynchronous (full duplex) * Synchronous - Master (half duplex) * Synchronous - Slave (half duplex) The SPEN (RCSTA register) and the TRISC<7> bits have to be set, and the TRISC<6> bit must be cleared, in order to configure pins RC6/TX/CK and RC7/RX/DT as the Universal Synchronous Asynchronous Receiver Transmitter. Register 16-1 shows the Transmit Status and Control Register (TXSTA) and Register 16-2 shows the Receive Status and Control Register (TXSTA). The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI). The USART can be configured as a full duplex asynchronous system that can communicate with peripheral devices, such as CRT terminals and personal computers, or it can be configured as a half duplex synchronous system that can communicate with peripheral devices, such as A/D or D/A integrated circuits, Serial EEPROMs, etc. REGISTER 16-1: TXSTA REGISTER R/W-0 CSRC bit 7 R/W-0 TX9 R/W-0 TXEN R/W-0 SYNC U-0 -- R/W-0 BRGH R-1 TRMT R/W-0 TX9D bit 0 bit 7 CSRC: Clock Source Select bit Asynchronous mode Don't care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6 TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode Unimplemented: Read as '0' BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode bit 5 bit 4 bit 3 bit 2 bit 1 TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full TX9D: 9th bit of transmit data. Can be Address/Data bit or a parity bit. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 167 PIC18CXX8 REGISTER 16-2: RCSTA REGISTER R/W-0 SPEN bit 7 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception SREN: Single Receive Enable bit Asynchronous mode Don't care Synchronous mode - Master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - Slave Unused in this mode bit 4 CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3 ADDEN: Address Detect Enable bit Asynchronous mode 9-bit (RX9 = 1) 1 = Enables address detection, enable interrupt and load of the receive buffer when RSR<8> is set 0 = Disables address detection, all bytes are received, and ninth bit can be used as parity bit FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error RX9D: 9th bit of received data, can be Address/Data bit or a parity bit Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 RX9 R/W-0 SREN R/W-0 CREN R/W-0 ADDEN R-0 FERR R-0 OERR R-x RX9D bit 0 bit 6 bit 5 bit 2 bit 1 bit 0 DS30475A-page 168 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.1 USART Baud Rate Generator (BRG) The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA register) also controls the baud rate. In Synchronous mode, bit BRGH is ignored. Table 16-1 shows the formula for computation of the baud rate for different USART modes, which only apply in Master mode (internal clock). Given the desired baud rate and FOSC, the nearest integer value for the SPBRG register can be calculated using the formula in Table 16-1. From this, the error in baud rate can be determined. Example 16-1 shows the calculation of the baud rate error for the following conditions: FOSC = 16 MHz Desired Baud Rate = 9600 BRGH = 0 SYNC = 0 It may be advantageous to use the high baud rate (BRGH = 1), even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the baud rate error in some cases. Writing a new value to the SPBRG register causes the BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before outputting the new baud rate. 16.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. EXAMPLE 16-1: CALCULATING BAUD RATE ERROR Desired Baud Rate Solving for X: X X X Calculated Baud Rate Error = = = = = = = = ( (FOSC / Desired Baud Rate) / 64 ) - 1 ((16000000 / 9600) / 64) - 1 [25.042] = 25 16000000 / (64 (25 + 1)) 9615 (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate (9615 - 9600) / 9600 0.16% = FOSC / (64 (X + 1)) TABLE 16-1: SYNC 0 1 BAUD RATE FORMULA BRGH = 0 (Low Speed) (Asynchronous) Baud Rate = FOSC/(64(X+1)) (Synchronous) Baud Rate = FOSC/(4(X+1)) BRGH = 1 (High Speed) Baud Rate = FOSC/(16(X+1)) NA Legend: X = value in SPBRG (0 to 255) TABLE 16-2: Name TXSTA RCSTA SPBRG REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Bit 6 TX9 RX9 Bit 5 TXEN SREN Bit 4 SYNC CREN Bit 3 -- ADDEN Bit 2 BRGH FERR Bit 1 TRMT OERR Bit 0 TX9D RX9D Value on POR, BOR 0000 -010 0000 000x 0000 0000 Value on all other RESETS 0000 -010 0000 000x 0000 0000 Bit 7 CSRC SPEN Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used by the BRG. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 169 PIC18CXX8 TABLE 16-3: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR SYNCHRONOUS MODE SPBRG value (decimal) 129 103 32 19 0 255 SPBRG value (decimal) 207 51 41 12 7 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 33 MHz KBAUD NA NA NA NA NA 77.10 95.93 294.64 485.30 8250 32.23 % ERROR +0.39 -0.07 -1.79 -2.94 10 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 % ERROR +0.16 -1.36 +0.16 +4.17 0 SPBRG value (decimal) 106 85 27 16 0 255 SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 92 46 11 8 2 1 0 255 25 MHz KBAUD NA NA NA NA NA 77.16 96.15 297.62 480.77 6250 24.41 +0.47 +0.16 -0.79 -3.85 % ERROR SPBRG value (decimal) 80 64 20 12 0 255 SPBRG value (decimal) 185 92 22 18 5 3 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 20 MHz KBAUD NA NA NA NA NA 76.92 96.15 294.12 500 5000 19.53 % ERROR +0.16 +0.16 -1.96 0 SPBRG value (decimal) 64 51 16 9 0 255 SPBRG value (decimal) 131 65 16 12 3 2 0 255 SPBRG value (decimal) 26 6 2 0 0 255 FOSC = 40 MHz KBAUD NA NA NA NA NA 76.92 96.15 303.03 500 10000 39.06 % ERROR +0.16 +0.16 +1.01 0 - FOSC = 16 MHz KBAUD NA NA NA NA 19.23 76.92 95.24 307.70 500 4000 15.63 % ERROR +0.16 +0.16 -0.79 +2.56 0 - 7.15909 MHz KBAUD NA NA NA 9.62 19.24 77.82 94.20 298.35 447.44 1789.80 6.99 +0.23 +0.23 +1.32 -1.88 -0.57 -10.51 1 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 % ERROR % ERROR 5.0688 MHz KBAUD NA NA NA 9.60 19.20 74.54 97.48 316.80 422.40 1267.20 4.95 % ERROR 0 0 -2.94 +1.54 +5.60 -15.52 - FOSC = 4 MHz KBAUD NA NA NA 9.62 19.23 76.92 1000 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 - 3.579545 MHz KBAUD NA NA NA 9.62 19.04 74.57 99.43 298.30 447.44 894.89 3.50 % ERROR +0.23 -0.83 -2.90 +3.57 -0.57 -10.51 - 32.768 kHz KBAUD 0.30 1.17 2.73 8.20 NA NA NA NA NA 8.20 0.03 % ERROR +1.14 -2.48 +13.78 -14.67 - DS30475A-page 170 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 16-4: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 207 103 25 12 2 2 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 33 MHz KBAUD NA NA 2.40 9.55 19.10 73.66 103.13 257.81 NA 515.63 2.01 -0.07 -0.54 -0.54 -4.09 +7.42 -14.06 10 MHz KBAUD NA 1.20 2.40 9.77 19.53 78.13 78.13 156.25 NA 156.25 0.61 +0.16 +0.16 +1.73 +1.73 +1.73 -18.62 -47.92 % ERROR % ERROR SPBRG value (decimal) 214 53 26 6 4 1 0 255 SPBRG value (decimal) 129 64 15 7 1 1 0 0 255 SPBRG value (decimal) 185 46 22 5 2 0 0 255 25 MHz KBAUD NA NA 2.40 9.53 19.53 78.13 97.66 NA NA 390.63 1.53 -0.15 -0.76 +1.73 +1.73 +1.73 % ERROR SPBRG value (decimal) 162 40 19 4 3 0 255 SPBRG value (decimal) 92 46 11 5 0 0 255 SPBRG value (decimal) 51 12 6 1 0 0 255 20 MHz KBAUD NA NA 2.40 9.47 19.53 78.13 104.17 312.50 NA 312.50 1.22 % ERROR +0.16 -1.36 +1.73 +1.73 +8.51 +4.17 SPBRG value (decimal) 129 32 15 3 2 0 0 255 SPBRG value (decimal) 65 32 7 3 0 0 255 SPBRG value (decimal) 1 0 255 FOSC = 40 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 % ERROR FOSC = 16 MHz KBAUD NA 1.20 2.40 9.62 19.23 83.33 83.33 250 NA 250 0.98 +0.16 +0.16 +0.16 +0.16 +8.51 -13.19 -16.67 % ERROR 7.15909 MHz KBAUD NA 1.20 2.38 9.32 18.64 111.86 NA NA NA 111.86 0.44 +0.23 -0.83 -2.90 -2.90 +45.65 1 MHz KBAUD 0.30 1.20 2.23 7.81 15.63 NA NA NA NA 15.63 0.06 % ERROR +0.16 +0.16 -6.99 -18.62 -18.62 % ERROR 5.0688 MHz KBAUD NA 1.20 2.40 9.90 19.80 79.20 NA NA NA 79.20 0.31 % ERROR 0 0 +3.13 +3.13 +3.13 32.768 kHz KBAUD 0.26 NA NA NA NA NA NA NA NA 0.51 0.002 % ERROR -14.67 - FOSC = 4 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR -0.16 +1.67 +1.67 -6.99 +8.51 -18.62 - 3.579545 MHz KBAUD 0.30 1.19 2.43 9.32 18.64 55.93 NA NA NA 55.93 0.22 % ERROR +0.23 -0.83 +1.32 -2.90 -2.90 -27.17 - 2000 Microchip Technology Inc. Advanced Information DS30475A-page 171 PIC18CXX8 TABLE 16-5: BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATE (Kbps) 0.3 1.2 2.4 9.6 19.2 76.8 96 300 500 HIGH LOW BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1) SPBRG value (decimal) 129 32 25 7 4 0 255 SPBRG value (decimal) 103 51 12 9 2 1 0 255 SPBRG value (decimal) 207 103 25 12 0 255 33 MHz KBAUD NA NA NA 9.60 19.28 76.39 98.21 294.64 515.63 2062.50 8,06 -0.07 +0.39 -0.54 +2.31 -1.79 +3.13 10 MHz KBAUD NA NA NA 9.62 18.94 78.13 89.29 312.50 625 625 2.44 % ERROR +0.16 -1.36 +1.73 -6.99 +4.17 +25.00 % ERROR 214 106 26 20 6 3 0 255 SPBRG value (decimal) 64 32 7 6 1 0 0 255 SPBRG value (decimal) 185 92 22 11 2 1 0 0 255 SPBRG value (decimal) 25 MHz KBAUD NA NA NA 9.59 19.30 78.13 97.66 312.50 520.83 1562.50 6.10 -0.15 +0.47 +1.73 +1.73 +4.17 +4.17 % ERROR 162 80 19 15 4 2 0 255 SPBRG value (decimal) 185 46 22 5 4 0 0 0 255 SPBRG value (decimal) 207 51 25 6 2 0 0 255 SPBRG value (decimal) 20 MHz KBAUD NA NA NA 9.62 19.23 78.13 96.15 312.50 416.67 1250 4.88 +0.16 +0.16 +1.73 +0.16 +4.17 -16.67 % ERROR SPBRG value (decimal) 129 64 15 12 3 2 0 255 SPBRG value (decimal) 131 32 16 3 2 0 0 255 SPBRG value (decimal) 6 1 0 0 255 FOSC = 40 MHz KBAUD NA NA NA NA 19.23 75.76 96.15 312.50 500 2500 9.77 +0.16 -1.36 +0.16 +4.17 0 % ERROR FOSC = 16 MHz KBAUD NA NA NA 9.62 19.23 76.92 100 333.33 500 1000 3.91 % ERROR +0.16 +0.16 +0.16 +4.17 +11.11 0 - 7.15909 MHz KBAUD NA NA 2.41 9.52 19.45 74.57 89.49 447.44 447.44 447.44 1.75 % ERROR +0.23 -0.83 +1.32 -2.90 -6.78 +49.15 -10.51 1 MHz KBAUD 0.30 1.20 2.40 8.93 20.83 62.50 NA NA NA 62.50 0.24 % ERROR +0.16 +0.16 +0.16 -6.99 +8.51 -18.62 - 5.0688 MHz KBAUD NA NA 2.40 9.60 18.64 79.20 105.60 316.80 NA 316.80 1.24 % ERROR 0 0 -2.94 +3.13 +10.00 +5.60 - FOSC = 4 MHz KBAUD NA 1.20 2.40 9.62 19.23 NA NA NA NA 250 0.98 % ERROR +0.16 +0.16 +0.16 +0.16 - 3.579545 MHz KBAUD NA 1.20 2.41 9.73 18.64 74.57 111.86 223.72 NA 55.93 0.22 % ERROR +0.23 +0.23 +1.32 -2.90 -2.90 +16.52 -25.43 - 32.768 kHz KBAUD 0.29 1.02 2.05 NA NA NA NA NA NA 2.05 0.008 % ERROR -2.48 -14.67 -14.67 - DS30475A-page 172 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.2 USART Asynchronous Mode In this mode, the USART uses standard non-return-to-zero (NRZ) format (one START bit, eight or nine data bits and one STOP bit). The most common data format is 8-bits. An on-chip dedicated 8-bit baud rate generator can be used to derive standard baud rate frequencies from the oscillator. The USART transmits and receives the LSb first. The USART's transmitter and receiver are functionally independent, but use the same data format and baud rate. The baud rate generator produces a clock, either x16 or x64 of the bit shift rate, depending on the BRGH bit (TXSTA register). Parity is not supported by the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is stopped during SLEEP. Asynchronous mode is selected by clearing the SYNC bit (TXSTA register). The USART Asynchronous module consists of the following important elements: * * * * Baud Rate Generator Sampling Circuit Asynchronous Transmitter Asynchronous Receiver USART ASYNCHRONOUS TRANSMITTER 3. 4. 5. 6. 7. Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR registers) is set. This interrupt can be enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicated the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. Status bit TRMT is a read only bit, which is set when the TSR register is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. Note 1: The TSR register is not mapped in data memory, so it is not available to the user. 2: Flag bit TXIF is set when enable bit TXEN is set. Steps to follow when setting up an Asynchronous Transmission: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 16.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set transmit bit TX9. Can be used as address/data bit. Enable the transmission by setting bit TXEN, which will also set bit TXIF. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Load data to the TXREG register (starts transmission). 2. 16.2.1 The USART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the Transmit (serial) Shift Register (TSR). The TSR register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been transmitted from the previous load. As soon as the STOP bit is transmitted, the TSR is loaded with new data from the TXREG register (if available). FIGURE 16-1: USART TRANSMIT BLOCK DIAGRAM Data Bus TXIF TXIE MSb (8) Interrupt TXEN Baud Rate CLK TRMT SPBRG Baud Rate Generator TX9 TX9D SPEN TXREG register 8 LSb *** TSR register 0 Pin Buffer and Control RC6/TX/CK pin 2000 Microchip Technology Inc. Advanced Information DS30475A-page 173 PIC18CXX8 FIGURE 16-2: ASYNCHRONOUS TRANSMISSION Write to TXREG BRG Output (shift clock) RC6/TX/CK (pin) TXIF bit (Transmit buffer register empty flag) Word 1 START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit TRMT bit (Transmit shift register empty flag) Word 1 Transmit Shift Reg FIGURE 16-3: ASYNCHRONOUS TRANSMISSION (BACK TO BACK) Write to TXREG BRG Output (shift clock) RC6/TX/CK (pin) TXIF bit (interrupt reg. flag) Word 1 Word 2 START Bit Bit 0 Bit 1 Word 1 Bit 7/8 STOP Bit START Bit Word 2 Bit 0 TRMT bit (Transmit shift reg. empty flag) Word 1 Transmit Shift Reg. Word 2 Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions. TABLE 16-6: Name REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION Bit 6 Bit 5 Bit 4 Bit 3 RBIE Bit 2 Bit 1 Bit 0 RBIF Value on POR, BOR Value on all other RESETS Bit 7 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE PIR1 PIE1 IPR1 RCSTA TXSTA PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN TXEN TXIF TXIE TXIP CREN TMR0IF INT0IF 0000 000x 0000 000u SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 SSPIP CCP1IP TMR2IP TMR1IP 0000 0000 0000 0000 -- FERR OERR TRMT RX9D TX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 0000 0010 0000 0010 0000 0000 0000 0000 TXREG USART Transmit Register SYNC ADDEN BRGH SPBRG Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. DS30475A-page 174 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.2.2 USART ASYNCHRONOUS RECEIVER 16.2.3 The receiver block diagram is shown in Figure 16-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high speed shifter, operating at x16 times the baud rate, whereas the main receive serial shifter operates at the bit rate or at FOSC. This mode would typically be used in RS-232 systems. Steps to follow when setting up an Asynchronous Reception: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is desired, set bit BRGH (Section 16.1). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. Enable the reception by setting bit CREN. Flag bit RCIF will be set when reception is complete and an interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing enable bit CREN. SETTING UP 9-BIT MODE WITH ADDRESS DETECT This mode would typically be used in RS-485 systems. Steps to follow when setting up an Asynchronous Reception with Address Detect Enable: 1. Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is required, set the BRGH bit. 2. Enable the asynchronous serial port by clearing the SYNC bit and setting the SPEN bit. 3. If interrupts are required, set the RCEN bit and select the desired priority level with the RCIP bit. 4. Set the RX9 bit to enable 9-bit reception. 5. Set the ADDEN bit to enable address detect. 6. Enable reception by setting the CREN bit. 7. The RCIF bit will be set when reception is complete. The interrupt will be acknowledged if the RCIE and GIE bits are set. 8. Read the RCSTA register to determine if any error occurred during reception, as well as read bit 9 of data (if applicable). 9. Read RCREG to determine if the device is being addressed. 10. If any error occurred, clear the CREN bit. 11. If the device has been addressed, clear the ADDEN bit to allow all received data into the receive buffer and interrupt the CPU. 2. 3. 4. 5. 6. 7. 8. 9. FIGURE 16-4: USART RECEIVE BLOCK DIAGRAM x64 Baud Rate CLK CREN SPBRG OERR FERR Baud Rate Generator RC7/RX/DT Pin Buffer and Control Data Recovery / 64 or / 16 MSb STOP (8) 7 RSR Register LSb 0 START *** 1 RX9 SPEN RX9D RCREG Register FIFO 8 Interrupt RCIF RCIE Data Bus Note: I/O pins have diode protection to VDD and VSS. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 175 PIC18CXX8 FIGURE 16-5: ASYNCHRONOUS RECEPTION RX (pin) Rcv shift reg Rcv buffer reg Read Rcv buffer reg RCREG RCIF (interrupt flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. START bit bit0 bit1 bit7/8 STOP bit START bit bit0 bit7/8 STOP bit START bit bit7/8 STOP bit Word 1 RCREG Word 2 RCREG TABLE 16-7: Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN Bit 3 RBIE SSPIF SSPIE SSPIP -- Bit 2 TMR0IF Bit 1 INT0IF Bit 0 RBIF TMR1IF Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 TXEN SYNC ADDEN BRGH TRMT TX9D 0000 0010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE PSPIF PSPIE PSPIP SPEN ADIF ADIE ADIP RX9 RCIF RCIE RCIP SREN CCP1IF TMR2IF CCP1IE TMR2IE TMR1IE CCP1IP TMR2IP TMR1IP FERR OERR RX9D USART Receive Register CSRC TX9 Baud Rate Generator Register Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. DS30475A-page 176 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit SYNC (TXSTA register). In addition, enable bit SPEN (RCSTA register) is set, in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively. The Master mode indicates that the processor transmits the master clock on the CK line. The Master mode is entered by setting bit CSRC (TXSTA register). 16.3.1 USART SYNCHRONOUS MASTER TRANSMISSION enabled/disabled by setting/clearing enable bit TXIE (PIE registers). Flag bit TXIF will be set, regardless of the state of enable bit TXIE, and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit TRMT (TXSTA register) shows the status of the TSR register. TRMT is a read only bit, which is set when the TSR is empty. No interrupt logic is tied to this bit, so the user has to poll this bit in order to determine if the TSR register is empty. The TSR is not mapped in data memory, so it is not available to the user. Steps to follow when setting up a Synchronous Master Transmission: 1. 2. 3. 4. 5. 6. 7. Initialize the SPBRG register for the appropriate baud rate (Section 16.1). Enable the synchronous master serial port by setting bits SYNC, SPEN, and CSRC. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. The USART transmitter block diagram is shown in Figure 16-1. The heart of the transmitter is the Transmit (serial) Shift register (TSR). The shift register obtains its data from the Read/Write Transmit Buffer register (TXREG). The TXREG register is loaded with data in software. The TSR register is not loaded until the last bit has been transmitted from the previous load. As soon as the last bit is transmitted, the TSR is loaded with new data from the TXREG (if available). Once the TXREG register transfers the data to the TSR register (occurs in one TCY), the TXREG is empty and interrupt bit TXIF (PIR registers) is set. The interrupt can be TABLE 16-8: Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 6 PEIE/GIEL ADIF ADIE ADIP RX9 TX9 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PSPIF PSPIE PSPIP SPEN CSRC USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 177 PIC18CXX8 FIGURE 16-6: SYNCHRONOUS TRANSMISSION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to TXREG reg Write Word 1 Bit 0 Bit 1 Word 1 Bit 2 Bit 7 Bit 0 Bit 1 Word 2 Bit 7 Write Word 2 TXIF bit (Interrupt flag) TRMT bit TRMT '1' '1' TXEN bit Note: Sync Master mode; SPBRG = '0'; continuous transmission of two 8-bit words. FIGURE 16-7: SYNCHRONOUS TRANSMISSION (THROUGH TXEN) RC7/RX/DT pin RC6/TX/CK pin bit0 bit1 bit2 bit6 bit7 Write to TXREG reg TXIF bit TRMT bit TXEN bit DS30475A-page 178 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 16.3.2 USART SYNCHRONOUS MASTER RECEPTION Steps to follow when setting up a Synchronous Master Reception: 1. Initialize the SPBRG register for the appropriate baud rate (Section 16.1). 2. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. 3. Ensure bits CREN and SREN are clear. 4. If interrupts are desired, set enable bit RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. If a single reception is required, set bit SREN. For continuous reception, set bit CREN. 7. Interrupt flag bit RCIF will be set when reception is complete and an interrupt will be generated if the enable bit RCIE was set. 8. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. 9. Read the 8-bit received data by reading the RCREG register. 10. If any error occurred, clear the error by clearing bit CREN. Once Synchronous Master mode is selected, reception is enabled by setting either enable bit SREN (RCSTA register), or enable bit CREN (RCSTA register). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock. If enable bit SREN is set, only a single word is received. If enable bit CREN is set, the reception is continuous until CREN is cleared. If both bits are set, then CREN takes precedence. TABLE 16-9: Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 6 Bit 5 TMR0IE RCIF RCIE RCIP SREN TXEN Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 USART Receive Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Reception. FIGURE 16-8: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin RC6/TX/CK pin Write to bit SREN SREN bit CREN bit RCIF bit '0' bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 '0' (interrupt) Read RXREG Note: Timing diagram demonstrates SYNC Master mode with bit SREN = '1' and bit BRGH = '0'. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 179 PIC18CXX8 16.4 USART Synchronous Slave Mode 16.4.2 USART SYNCHRONOUS SLAVE RECEPTION Synchronous Slave mode differs from the Master mode, in that the shift clock is supplied externally at the RC6/TX/CK pin (instead of being supplied internally in Master mode). This allows the device to transfer or receive data while in SLEEP mode. Slave mode is entered by clearing bit CSRC (TXSTA register). 16.4.1 USART SYNCHRONOUS SLAVE TRANSMIT The operation of the Synchronous Master and Slave modes is identical, except in the case of the SLEEP mode and bit SREN, which is a "don't care" in Slave mode. If receive is enabled by setting bit CREN prior to the SLEEP instruction, then a word may be received during SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register, and if enable bit RCIE bit is set, the interrupt generated will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. Steps to follow when setting up a Synchronous Slave Reception: 1. Enable the synchronous master serial port by setting bits SYNC and SPEN and clearing bit CSRC. If interrupts are desired, set enable bit RCIE. If 9-bit reception is desired, set bit RX9. To enable reception, set enable bit CREN. Flag bit RCIF will be set when reception is complete. An interrupt will be generated if enable bit RCIE was set. Read the RCSTA register to get the ninth bit (if enabled) and determine if any error occurred during reception. Read the 8-bit received data by reading the RCREG register. If any error occurred, clear the error by clearing bit CREN. The operation of the Synchronous Master and Slave modes are identical, except in the case of the SLEEP mode. If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: a) b) c) d) The first word will immediately transfer to the TSR register and transmit. The second word will remain in TXREG register. Flag bit TXIF will not be set. When the first word has been shifted out of TSR, the TXREG register will transfer the second word to the TSR and flag bit TXIF will be set. If enable bit TXIE is set, the interrupt will wake the chip from SLEEP. If the global interrupt is enabled, the program will branch to the interrupt vector. 2. 3. 4. 5. e) 6. Steps to follow when setting up a Synchronous Slave Transmission: 1. Enable the synchronous slave serial port by setting bits SYNC and SPEN and clearing bit CSRC. Clear bits CREN and SREN. If interrupts are desired, set enable bit TXIE. If 9-bit transmission is desired, set bit TX9. Enable the transmission by setting enable bit TXEN. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. Start transmission by loading data to the TXREG register. 7. 8. 2. 3. 4. 5. 6. 7. DS30475A-page 180 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 16-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name INTCON PIR1 PIE1 IPR1 RCSTA TXREG TXSTA SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 TXEN 0000 0010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN USART Transmit Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave transmission. TABLE 16-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION Name INTCON PIR1 PIE1 IPR1 RCSTA RCREG TXSTA SPBRG Bit 7 Bit 6 Bit 5 Bit 4 INT0IE TXIF TXIE TXIP CREN SYNC Bit 3 RBIE SSPIF SSPIE SSPIP -- ADDEN Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP FERR BRGH Bit 1 INT0IF TMR2IF TMR2IE TMR2IP OERR TRMT Bit 0 RBIF TMR1IF TMR1IE TMR1IP RX9D TX9D Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 TXEN 0000 0010 0000 0000 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 0000 -00x 0000 0000 0000 0010 0000 0000 GIE/GIEH PEIE/GIEL TMR0IE PSPIF PSPIE PSPIP SPEN CSRC ADIF ADIE ADIP RX9 TX9 RCIF RCIE RCIP SREN USART Receive Register Baud Rate Generator Register Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Slave reception. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 181 PIC18CXX8 NOTES: DS30475A-page 182 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.0 17.1 CAN MODULE Overview 17.1.1 OVERVIEW OF THE MODULE The Controller Area Network (CAN) module is a serial interface, useful for communicating with other peripherals or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. The CAN module is a communication controller implementing the CAN 2.0 A/B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN2.0B Passive, and CAN 2.0B Active versions of the protocol. The module implementation is a Full CAN system. The CAN specification is not covered within this data sheet. The reader may refer to the BOSCH CAN specification for further details. The module features are as follows: * Implementation of the CAN protocol CAN1.2, CAN2.0A and CAN2.0B * Standard and extended data frames * 0 - 8 bytes data length * Programmable bit rate up to 1 Mbit/sec * Support for remote frames * Double buffered receiver with two prioritized received message storage buffers * 6 full (standard/extended identifier) acceptance filters, 2 associated with the high priority receive buffer, and 4 associated with the low priority receive buffer * 2 full acceptance filter masks, one each associated with the high and low priority receive buffers * Three transmit buffers with application specified prioritization and abort capability * Programmable wake-up functionality with integrated low-pass filter * Programmable Loopback mode supports self-test operation * Signaling via interrupt capabilities for all CAN receiver and transmitter error states * Programmable clock source * Programmable link to timer module for time-stamping and network synchronization * Low power SLEEP mode The CAN bus module consists of a Protocol Engine and message buffering and control. The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the 2 receive registers. The CAN Module supports the following Frame types: * * * * * * Standard Data Frame Extended Data Frame Remote Frame Error Frame Overload Frame Reception Interframe Space 2000 Microchip Technology Inc. Advanced Information DS30475A-page 183 PIC18CXX8 17.1.2 TRANSMIT/RECEIVE BUFFERS The PIC18CXX8 has three transmit and two receive buffers, two acceptance masks (one for each receive buffer), and a total of six acceptance filters. Figure 17-1 is a block diagram of these buffers and their connection to the protocol engine. FIGURE 17-1: CAN BUFFERS AND PROTOCOL ENGINE BLOCK DIAGRAM Acceptance Mask RXM1 Acceptance Filter RXF2 TXB0 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB1 MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF TXB2 A c c e p t MESSAGE MSGREQ TXABT TXLARB TXERR MTXBUFF Acceptance Mask RXM0 Acceptance Filter RXF0 Acceptance Filter RXF1 Acceptance Filter RXF3 Acceptance Filter RXF4 Acceptance Filter RXF5 A c c e p t BUFFERS Message Queue Control R X B 0 Transmit Byte Sequencer Identifier M A B Identifier R X B 1 Data Field Data Field PROTOCOL ENGINE Transmit Shift Receive Shift Receive Error Counter RXERRCNT TXERRCNT ErrPas BusOff Transmit Error Counter CRC Generator CRC Check Protocol Finite State Machine Transmit Logic Bit Timing Logic Bit Timing Generator TX RX DS30475A-page 184 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.2 Note: Control Registers for the CAN Module Not all CAN registers are available in the access bank. 17.2.1 CAN CONTROL AND STATUS REGISTERS This section shows the CAN Control and Status registers. There are many registers associated with the CAN module. Descriptions of these registers are grouped into sections. These sections are: * * * * * Control and Status Registers Transmit Buffer Registers Receive Buffer Registers Baud Rate Control Registers Interrupt Status and Control Registers REGISTER 17-1: CANCON - CAN CONTROL REGISTER R/W-1 REQOP2 bit 7 R/W-0 REQOP1 R/W-0 REQOP0 R/W-0 ABAT R/W-0 WIN2 R/W-0 WIN1 R/W-0 WIN0 U-0 -- bit 0 bit 7-5 REQOP2:REQOP0: Request CAN Operation Mode bits 1xx = Request Configuration mode 011 = Request Listen Only mode 010 = Request Loopback mode 001 = Request Disable mode 000 = Request Normal mode ABAT: Abort All Pending Transmissions bit 1 = Abort all pending transmissions (in all transmit buffers) 0 = Transmissions proceeding as normal WIN2:WIN0: Window Address bits This selects which of the CAN buffers to switch into the access bank area. This allows access to the buffer registers from any data memory bank. After a frame has caused an interrupt, the ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer. See Example 17-1 for code example. 111 = Receive Buffer 0 110 = Receive Buffer 0 101 = Receive Buffer 1 100 = Transmit Buffer 0 011 = Transmit Buffer 1 010 = Transmit Buffer 2 001 = Receive Buffer 0 000 = Receive Buffer 0 bit 4 bit 3-1 bit 0 Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 185 PIC18CXX8 REGISTER 17-2: CANSTAT - CAN STATUS REGISTER R-1 R-0 R-0 OPMODE2 OPMODE1 OPMODE0 bit 7 bit 7-5 OPMODE2:OPMODE0: Operation Mode Status bits 111 = Reserved 110 = Reserved 101 = Reserved 100 = Configuration mode 011 = Listen Only mode 010 = Loopback mode 001 = Disable mode 000 = Normal mode Note: bit 4 bit 3-1 Before the device goes into SLEEP mode, select Disable mode. U-0 -- R-0 ICODE2 R-0 ICODE1 R-0 ICODE0 U-0 -- bit 0 Unimplemented: Read as '0' ICODE2:ICODE0: Interrupt Code bits When an interrupt occurs, a prioritized coded interrupt value will be present in the ICODE2:ICODE0 bits. These codes indicate the source of the interrupt. The ICODE2:ICODE0 bits can be copied to the WIN2:WIN0 bits to select the correct buffer to map into the Access Bank area. See Example 17-1 for code example. 111 = Wake-up on Interrupt 110 = RXB0 Interrupt 101 = RXB1 Interrupt 100 = TXB0 Interrupt 011 = TXB1 Interrupt 010 = TXB2 Interrupt 001 = Error Interrupt 000 = No Interrupt Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 DS30475A-page 186 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 EXAMPLE 17-1: WIN AND ICODE BITS USAGE IN INTERRUPT SERVICE ROUTINE TO ACCESS TX/RX BUFFERS ; Save application required context. ; Poll interrupt flags and determine source of interrupt ; This was found to be CAN interrupt ; TempCANCON and TempCANSTAT are variables defined in Access Bank low movff CANCON, TempCANCON ; Save CANCON.WIN bits ; This is required to prevent CANCON ; from corrupting CAN buffer access ; in-progress while this interrupt ; occurred movff CANSTAT, TempCANSTAT ; ; ; ; ; Save CANSTAT register This is required to make sure that we use same CANSTAT value rather than one changed by another CAN interrupt. movf andlw addwf bra bra bra bra bra bra bra TempCANSTAT, W b'00001110' PCL, F NoInterrupt ErrorInterrupt TXB2Interrupt TXB1Interrupt TXB0Interrupt RXB1Interrupt RXB0Interrupt ; Retrieve ICODE bits ; Perform computed GOTO ; to corresponding interrupt cause ; ; ; ; ; ; ; ; 000 001 010 011 100 101 110 111 = = = = = = = = No interrupt Error interrupt TXB2 interrupt TXB1 interrupt TXB0 interrupt RXB1 interrupt RXB0 interrupt Wake-up on interrupt WakeupInterrupt bcf PIR3, WAKIF ; Clear the interrupt flag ; ; User code to handle wake-up procedure ; ; ; Continue checking for other interrupt source or return from here ... NoInterrupt ... ; PC should never vector here. User may ; place a trap such as infinite loop or pin/port ; indication to catch this error. ; Clear the interrupt flag ; Handle error. ErrorInterrupt bcf PIR3, ERRIF ... retfie TXB2Interrupt bcf PIR3, TXB2IF goto AccessBuffer TXB1Interrupt bcf PIR3, TXB1IF goto AccessBuffer TXB0Interrupt bcf PIR3, TXB0IF goto AccessBuffer RXB1Interrupt bcf PIR3, RXB1IF goto Accessbuffer ; Clear the interrupt flag ; Clear the interrupt flag ; Clear the interrupt flag ; Clear the interrupt flag 2000 Microchip Technology Inc. Advanced Information DS30475A-page 187 PIC18CXX8 RXB0Interrupt bcf PIR3, RXB0IF goto AccessBuffer ; Clear the interrupt flag AccessBuffer ; This is either TX or RX interrupt ; Copy CANCON.ICODE bits to CANSTAT.WIN bits movf TempCANCON, W ; Clear CANCON.WIN bits before copying ; new ones. andlw b'11110001' ; Use previously saved CANCON value to ; make sure same value. movwf TempCANCON ; Copy masked value back to TempCANCON movf andlw iorwf movff TempCANSTAT, W b'00001110' TempCANCON TempCANCON, CANCON ; Retrieve ICODE bits ; Use previously saved CANSTAT value ; to make sure same value. ; Copy ICODE bits to WIN bits. ; Copy the result to actual CANCON ; Access current buffer... ; Your code ; Restore CANCON.WIN bits movf CANCON, W andlw b'11110001' iorwf TempCANCON ; Preserve current non WIN bits ; Restore original WIN bits ; Do not need to restore CANSTAT - it is read-only register. ; Return from interrupt or check for another module interrupt source DS30475A-page 188 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-3: COMSTAT - COMMUNICATION STATUS REGISTER R/C-0 R/C-0 RXB0OVFL RXB1OVFL bit 7 bit 7 RXB0OVFL: Receive Buffer 0 Overflow bit 1 = Receive Buffer 0 overflowed 0 = Receive Buffer 0 has not overflowed RXB1OVFL: Receive Buffer 1 Overflow bit 1 = Receive Buffer 1 overflowed 0 = Receive Buffer 1 has not overflowed TXB0: Transmitter Bus Off bit 1 = Transmit Error Counter >255 0 = Transmit Error Counter 255 TXBP: Transmitter Bus Passive bit 1 = Transmission Error Counter >127 0 = Transmission Error Counter 127 RXBP: Receiver Bus Passive bit 1 = Receive Error Counter >127 0 = Receive Error Counter 127 TXWARN: Transmitter Warning bit 1 = Transmit Error Counter >95 0 = Transmit Error Counter 95 RXWARN: Receiver Warning bit 1 = Receive Error Counter >95 0 = Receive Error Counter 95 EWARN: Error Warning bit This bit is a flag of the RXWARN and TXWARN bits 1 = The RXWARN or the TXWARN bits are set 0 = Neither the RXWARN or the TXWARN bits are set Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 TXBO R-0 TXBP R-0 RXBP R-0 R-0 R-0 TXWARN RXWARN EWARN bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 189 PIC18CXX8 17.2.2 CAN TRANSMIT BUFFER REGISTERS This section describes the CAN Transmit Buffer Register and the associated Transmit Buffer Control Registers. REGISTER 17-4: TXBnCON - TRANSMIT BUFFER n CONTROL REGISTER U-0 -- bit 7 R-0 TXABT R-0 TXLARB R-0 TXERR R/W-0 TXREQ U-0 -- R/W-0 TXPRI1 R/W-0 TXPRI0 bit 0 bit 7 bit 6 Unimplemented: Read as '0' TXABT: Transmission Aborted Status bit 1 = Message was aborted 0 = Message was not aborted TXLARB: Transmission Lost Arbitration Status bit 1 = Message lost arbitration while being sent 0 = Message did not lose arbitration while being sent TXERR: Transmission Error Detected Status bit 1 = A bus error occurred while the message was being sent 0 = A bus error did not occur while the message was being sent TXREQ: Transmit Request Status bit 1 = Requests sending a message. Clears the TXABT, TLARB, and TXERR bits 0 = Automatically cleared when the message is successfully sent Note: Clearing this bit in software, while the bit is set, will request a message abort. bit 5 bit 4 bit 3 bit 2 bit 1-0 Unimplemented: Read as '0' TXPRI1:TXPRI0: Transmit Priority bits 11 = Priority Level 3 (Highest Priority) 10 = Priority Level 2 01 = Priority Level 1 00 = Priority Level 0 (Lowest Priority) Note: These bits set the order in which Transmit buffer will be transferred. They do not alter CAN message identifier. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 17-5: TXBnSIDH: TRANSMIT BUFFER n STANDARD IDENTIFIER HIGH BYTE REGISTER R/W-x SID10 bit 7 R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 bit 7-0 SID10:SID3: Standard Identifier bits, if EXIDE = 0 (TXBnSID Register). Extended Identifier bits EID28:EID21, if EXIDE = 1. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS30475A-page 190 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-6: TXBnSIDL - TRANSMIT BUFFER n STANDARD IDENTIFIER LOW BYTE REGISTER R/W-x SID2 bit 7 bit 7-5 bit 4 bit 3 SID2:SID0: Standard Identifier bits, if EXIDE = 0. Extended Identifier bits EID20:EID18, if EXIDE = 1. Unimplemented: Read as '0' EXIDE: Extended Identifier Enable bit 1 = Message will transmit Extended ID, SID10:SID0 becomes EID28:EID18 0 = Message will transmit Standard ID, EID17:EID0 are ignored Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 R/W-x -- R/W-x EXIDE R/W-x -- R/W-x EID17 R/W-x EID16 bit 0 bit 2 bit 1-0 REGISTER 17-7: TXBnEIDH - TRANSMIT BUFFER n EXTENDED IDENTIFIER HIGH BYTE REGISTER R/W-x EID15 bit 7 R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown REGISTER 17-8: TXBnEIDL - TRANSMIT BUFFER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x EID7 bit 7 R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 191 PIC18CXX8 REGISTER 17-9: TXBnDm - TRANSMIT BUFFER n DATA FIELD BYTE m REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x TXBnDm7 TXBnDm6 TXBnDm5 TXBnDm4 TXBnDm3 TXBnDm2 TXBnDm1 TXBnDm0 bit 7 bit 1-0 bit 0 TXBnDm7:TXBnDm0: Transmit Buffer n Data Field Byte m bits (where 0n<3 and 0 U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' TXRTR: Transmission Frame Remote Transmission Request bit 1 = Transmitted message will have TXRTR bit set 0 = Transmitted message will have TXRTR bit cleared. Unimplemented: Read as '0' DLC3:DLC0: Data Length Code bits 1111 = Reserved 1110 = Reserved 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x TXRTR U-0 -- U-0 -- R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 bit 5-4 bit 3-0 DS30475A-page 192 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-11: TXERRCNT - TRANSMIT ERROR COUNT REGISTER R-0 TEC7 bit 7 bit 7-0 R-0 TEC6 R-0 TEC5 R-0 TEC4 R-0 TEC3 R-0 TEC2 R-0 TEC1 R-0 TEC0 bit 0 TEC7:TEC0: Transmit Error Counter bits This register contains a value which is derived from the rate at which errors occur. When the error count overflows, the bus off state occurs. When the bus has 128 occurrences of 11 consecutive recessive bits, the counter value is cleared. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown 2000 Microchip Technology Inc. Advanced Information DS30475A-page 193 PIC18CXX8 17.2.3 CAN RECEIVE BUFFER REGISTERS This section shows the Receive Buffer registers with its associated control registers. REGISTER 17-12: RXB0CON - RECEIVE BUFFER 0 CONTROL REGISTER R/C-0 RXFUL bit 7 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. R/W-0 RXM1 R/W-0 RXM0 U-0 -- R-0 R/W-0 RXRTRRO RXB0DBEN R-0 JTOFF R/W-0 FILHIT0 bit 0 bit 6-5 RXM1:RXM0: Receive Buffer Mode bits 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages Unimplemented: Read as '0' RXRTRRO: Receive Remote Transfer Request Read Only bit 1 = Remote transfer request 0 = No remote transfer request RXB0DBEN: Receive Buffer 0 Double Buffer Enable bit 1 = Receive Buffer 0 overflow will write to Receive Buffer 1 0 = No Receive Buffer 0 overflow to Receive Buffer 1 JTOFF: Jump Table Offset bit (read only copy of RX0DBEN) 1 = Allows Jump Table offset between 6 and 7 0 = Allows Jump Table offset between 1 and 0 Note: This bit allows same filter jump table for both RXB0CON and RXB1CON. bit 4 bit 3 bit 2 bit 1 bit 0 FILHIT0: Filter Hit bit This bit indicates which acceptance filter enabled the message reception into receive buffer 0 1 = Acceptance Filter 1 (RXF1) 0 = Acceptance Filter 0 (RXF0) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS30475A-page 194 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-13: RXB1CON - RECEIVE BUFFER 1 CONTROL REGISTER R/C-0 RXFUL bit 7 bit 7 RXFUL: Receive Full Status bit 1 = Receive buffer contains a received message 0 = Receive buffer is open to receive a new message Note: This bit is set by the CAN module and should be cleared by software after the buffer is read. R/W-0 RXM1 R/W-0 RXM0 U-0 -- R-0 RXRTRRO R-0 FILHIT2 R-0 FILHIT1 R-0 FILHIT0 bit 0 bit 6-5 RXM1:RXM0: Receive Buffer Mode bits 11 = Receive all messages (including those with errors) 10 = Receive only valid messages with extended identifier 01 = Receive only valid messages with standard identifier 00 = Receive all valid messages Unimplemented: Read as '0' RXRTRRO: Receive Remote Transfer Request bit (read only) 1 = Remote transfer request 0 = No remote transfer request FILHIT2:FILHIT0: Filter Hit bits These bits indicate which acceptance filter enabled the last message reception into Receive Buffer 1. 111 = Reserved 110 = Reserved 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) only possible when RXB0DBEN bit is set 000 = Acceptance Filter 0 (RXF0) only possible when RXB0DBEN bit is set Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2-0 REGISTER 17-14: RXBnSIDH - RECEIVE BUFFER n STANDARD IDENTIFIER HIGH BYTE REGISTER R/W-x SID10 bit 7 bit 7-0 SID10:SID3: Standard Identifier bits, if EXID = 0 (RXBnSIDL Register). Extended Identifier bits EID28:EID21, if EXID = 1. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 195 PIC18CXX8 REGISTER 17-15: RXBnSIDL - RECEIVE BUFFER n STANDARD IDENTIFIER LOW BYTE REGISTER R/W-x SID2 bit 7 bit 7-5 bit 4 SID2:SID0: Standard Identifier bits, if EXID = 0. Extended Identifier bits EID20:EID18, if EXID = 1. SRR: Substitute Remove Request bit (only when EXID = '1') 1 = Remote transfer request occurred 0 = No remote transfer request occurred EXID: Extended Identifier bit 1 = Received message is an Extended Data Frame, SID10:SID0 are EID28:EID18 0 = Received message is a Standard Data Frame Unimplemented: Read as '0' EID17:EID16: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 R/W-x SRR R/W-x EXID U-0 -- R/W-x EID17 R/W-x EID16 bit 0 bit 3 bit 2 bit 1-0 REGISTER 17-16: RXBnEIDH - RECEIVE BUFFER n EXTENDED IDENTIFIER HIGH BYTE REGISTER R/W-x EID15 bit 7 bit 7-0 EID15:EID8: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 REGISTER 17-17: RXBnEIDL - RECEIVE BUFFER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x EID7 bit 7 bit 7-0 EID7:EID0: Extended Identifier bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 DS30475A-page 196 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-18: RXBnDLC - RECEIVE BUFFER n DATA LENGTH CODE REGISTER U-x -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' RXRTR: Receiver Remote Transmission Request bit 1 = Remote transfer request 0 = No remote transfer request RB1: Reserved bit 1 Reserved by CAN Spec and read as '0' RB0: Reserved bit 0 Reserved by CAN Spec and read as '0' DLC3:DLC0: Data Length Code bits 1111 = Invalid 1110 = Invalid 1101 = Invalid 1100 = Invalid 1011 = Invalid 1010 = Invalid 1001 = Invalid 1000 = Data Length = 8 bytes 0111 = Data Length = 7 bytes 0110 = Data Length = 6 bytes 0101 = Data Length = 5 bytes 0100 = Data Length = 4 bytes 0011 = Data Length = 3 bytes 0010 = Data Length = 2 bytes 0001 = Data Length = 1 bytes 0000 = Data Length = 0 bytes Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x RXRTR R/W-x RB1 R/W-x RB0 R/W-x DLC3 R/W-x DLC2 R/W-x DLC1 R/W-x DLC0 bit 0 bit 5 bit 4 bit 3-0 REGISTER 17-19: RXBnDm - RECEIVE BUFFER n DATA FIELD BYTE m REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RXBnDm7 RXBnDm6 RXBnDm5 RXBnDm4 RXBnDm3 RXBnDm2 RXBnDm1 RXBnDm0 bit 7 bit 7-0 bit 0 RXBnDm7:RXBnDm0: Receive Buffer n Data Field Byte m bits (where 0n<1 and 0 Advanced Information DS30475A-page 197 PIC18CXX8 REGISTER 17-20: RXERRCNT - RECEIVE ERROR COUNT REGISTER R-0 REC7 bit 7 bit 7-0 REC7:REC0: Receive Error Counter bits This register contains the Receive Error value as defined by the CAN specifications. When RXERRCNT > 127, the module will go into an error passive state. RXERRCNT does not have the ability to put the module in "Bus Off" state. Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R-0 REC6 R-0 REC5 R-0 REC4 R-0 REC3 R-0 REC2 R-0 REC1 R-0 REC0 bit 0 DS30475A-page 198 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.2.4 MESSAGE ACCEPTANCE FILTERS This subsection describes the Message Acceptance filters. REGISTER 17-21: RXFnSIDH - RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER HIGH BYTE R/W-x SID10 bit 7 bit 7-0 SID10:SID3: Standard Identifier Filter bits, if EXIDEN = 0. Extended Identifier Filter bits EID28:EID21, if EXIDEN = 1, Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 REGISTER 17-22: RXFnSIDL - RECEIVE ACCEPTANCE FILTER n STANDARD IDENTIFIER FILTER LOW BYTE R/W-x SID2 bit 7 bit 7-5 bit 4 bit 3 SID2:SID0: Standard Identifier Filter bits, if EXIDEN = 0. Extended Identifier Filter bits EID20:EID18, if EXIDEN = 0. Unimplemented: Read as '0' EXIDEN: Extended Identifier Filter Enable bit 1 = Filter will only accept Extended ID messages 0 = Filter will only accept Standard ID messages Unimplemented: Read as '0' EID17:EID16: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 U-0 -- R/W-x EXIDEN U-0 -- R/W-x EID17 R/W-x EID16 bit 0 bit 2 bit 1-0 REGISTER 17-23: RXFnEIDH - RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER HIGH BYTE R/W-x EID15 bit 7 bit 7-0 EID15:EID8: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 199 PIC18CXX8 REGISTER 17-24: RXFnEIDL - RECEIVE ACCEPTANCE FILTER n EXTENDED IDENTIFIER LOW BYTE REGISTER R/W-x EID7 bit 7 bit 7-0 EID7:EID0: Extended Identifier Filter bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 REGISTER 17-25: RXMnSIDH - RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK HIGH BYTE REGISTER R/W-x SID10 bit 7 bit 7-0 SID10:SID3: Standard Identifier Mask bits, or Extended Identifier Mask bits EID28:EID21 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID9 R/W-x SID8 R/W-x SID7 R/W-x SID6 R/W-x SID5 R/W-x SID4 R/W-x SID3 bit 0 REGISTER 17-26: RXMnSIDL - RECEIVE ACCEPTANCE MASK n STANDARD IDENTIFIER MASK LOW BYTE REGISTER R/W-x SID2 bit 7 bit 7-5 bit 4-2 bit 1-0 SID2:SID0: Standard Identifier Mask bits, or Extended Identifier Mask bits EID20:EID18 Unimplemented: Read as '0' EID17:EID16: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x SID1 R/W-x SID0 U-0 -- U-0 -- U-0 -- R/W-x EID17 R/W-x EID16 bit 0 DS30475A-page 200 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-27: RXMnEIDH - RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK HIGH BYTE REGISTER R/W-x EID15 bit 7 bit 1-0 EID15:EID8: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID14 R/W-x EID13 R/W-x EID12 R/W-x EID11 R/W-x EID10 R/W-x EID9 R/W-x EID8 bit 0 REGISTER 17-28: RXMnEIDL - RECEIVE ACCEPTANCE MASK n EXTENDED IDENTIFIER MASK LOW BYTE REGISTER R/W-x EID7 bit 7 bit 1-0 EID7:EID0: Extended Identifier Mask bits Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-x EID6 R/W-x EID5 R/W-x EID4 R/W-x EID3 R/W-x EID2 R/W-x EID1 R/W-x EID0 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 201 PIC18CXX8 17.2.5 CAN BAUD RATE REGISTERS This subsection describes the CAN Baud Rate registers. REGISTER 17-29: BRGCON1 - BAUD RATE CONTROL REGISTER 1 R/W-0 SJW1 bit 7 bit 7-6 SJW1:SJW0: Synchronized Jump Width bits 11 = Synchronization Jump Width Time = 4 x TQ 10 = Synchronization Jump Width Time = 3 x TQ 01 = Synchronization Jump Width Time = 2 x TQ 00 = Synchronization Jump Width Time = 1 x TQ BRP5:BRP0: Baud Rate Prescaler bits 111111 = TQ = (2 x 64)/FOSC 111110 = TQ = (2 x 63)/FOSC : : 000001 = TQ = (2 x 2)/FOSC 000000 = TQ = (2 x 1)/FOSC Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 SJW0 R/W-0 BRP5 R/W-0 BRP4 R/W-0 BRP3 R/W-0 BRP2 R/W-0 BRP1 R/W-0 BRP0 bit 0 bit 5-0 Note: This register is only accessible in Configuration mode. DS30475A-page 202 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-30: BRGCON2 - BAUD RATE CONTROL REGISTER 2 R/W-0 SEG2PHTS bit 7 bit 7 SEG2PHTS: Phase Segment 2 Time Select bit 1 = Freely programmable 0 = Maximum of PHEG1 or Information Processing Time (IPT), whichever is greater SAM: Sample of the CAN Bus Line bit 1 = Bus line is sampled three times prior to the sample point 0 = Bus line is sampled once at the sample point SEG1PH2:SEG1PH0: Phase Segment 1 bits 111 = Phase Segment 1 Time = 8 x TQ 110 = Phase Segment 1 Time = 7 x TQ 101 = Phase Segment 1 Time = 6 x TQ 100 = Phase Segment 1 Time = 5 x TQ 011 = Phase Segment 1 Time = 4 x TQ 010 = Phase Segment 1 Time = 3 x TQ 001 = Phase Segment 1 Time = 2 x TQ 000 = Phase Segment 1 Time = 1 x TQ PRSEG2:PRSEG0: Propagation Time Select bits 111 = Propagation Time = 8 x TQ 110 = Propagation Time = 7 x TQ 101 = Propagation Time = 6 x TQ 100 = Propagation Time = 5 x TQ 011 = Propagation Time = 4 x TQ 010 = Propagation Time = 3 x TQ 001 = Propagation Time = 2 x TQ 000 = Propagation Time = 1 x TQ Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 SAM R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SEG1PH2 SEG1PH1 SEG1PH0 PRSEG2 PRSEG1 R/W-0 PRSEG0 bit 0 bit 6 bit 5-3 bit 2-0 Note: This register is only accessible in Configuration mode. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 203 PIC18CXX8 REGISTER 17-31: BRGCON3 - BAUD RATE CONTROL REGISTER 3 U-0 -- bit 7 bit 7 bit 6 Unimplemented: Read as '0' WAKFIL: Selects CAN Bus Line Filter for Wake-up bit 1 = Use CAN bus line filter for wake-up 0 = CAN bus line filter is not used for wake-up Unimplemented: Read as '0' SEG2PH2:SEG2PH0: Phase Segment 2 Time Select bits 111 = Phase Segment 2 Time = 8 x TQ 110 = Phase Segment 2 Time = 7 x TQ 101 = Phase Segment 2 Time = 6 x TQ 100 = Phase Segment 2 Time = 5 x TQ 011 = Phase Segment 2 Time = 4 x TQ 010 = Phase Segment 2 Time = 3 x TQ 001 = Phase Segment 2 Time = 2 x TQ 000 = Phase Segment 2 Time = 1 x TQ Note: Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown Ignored if SEG2PHTS bit is clear. R/W-0 WAKFIL U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 R/W-0 SEG2PH2 SEG2PH1 SEG2PH0 bit 0 bit 5-3 bit 2-0 DS30475A-page 204 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.2.6 CAN MODULE I/O CONTROL REGISTER This subsection describes the CAN Module I/O Control register. REGISTER 17-32: CIOCON - CAN I/O CONTROL REGISTER R/W-0 TX1SRC bit 7 bit 7 TX1SRC: CAN TX1 Pin Data Source 1 = CAN TX1 pin will output the CAN clock 0 = CAN TX1 pin will output TXD TX1EN: CAN TX1 Pin Enable 1 = CAN TX1 pin will output TXD or CAN clock 0 = CAN TX1 pin will have digital I/O function ENDRHI: Enable Drive High 1 = CAN TX0, CAN TX1 pins will drive VDD when recessive 0 = CAN TX0, CAN TX1 pins will tri-state when recessive CANCAP: CAN Message Receive Capture Enable 1 = Enable CAN capture 0 = Disable CAN capture Unimplemented: Read as '0' Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 TX1EN R/W-0 ENDRHI R/W-0 CANCAP U-0 -- U-0 -- U-0 -- U-0 -- bit 0 bit 6 bit 5 bit 4 bit 3-0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 205 PIC18CXX8 17.2.7 CAN INTERRUPT REGISTERS REGISTER 17-33: PIR3 - PERIPHERAL INTERRUPT FLAG REGISTER R/W-0 IRXIF bit 7 bit 7 IRXIF: CAN Invalid Received Message Interrupt Flag bit 1 = An invalid message has occurred on the CAN bus 0 = No invalid message on CAN bus WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit 1 = Activity on CAN bus has occurred 0 = No activity on CAN bus ERRIF: CAN Bus Error Interrupt Flag bit 1 = An error has occurred in the CAN module (multiple sources) 0 = No CAN module errors TXB2IF: CAN Transmit Buffer 2 Interrupt Flag bit 1 = Transmit Buffer 2 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 2 has not completed transmission of a message TXB1IF: CAN Transmit Buffer 1 Interrupt Flag bit 1 = Transmit Buffer 1 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 1 has not completed transmission of a message TXB0IF: CAN Transmit Buffer 0 Interrupt Flag bit 1 = Transmit Buffer 0 has completed transmission of a message, and may be re-loaded 0 = Transmit Buffer 0 has not completed transmission of a message RXB1IF: CAN Receive Buffer 1 Interrupt Flag bit 1 = Receive Buffer 1 has received a new message 0 = Receive Buffer 1 has not received a new message RXB0IF: CAN Receive Buffer 0 Interrupt Flag bit 1 = Receive Buffer 0 has received a new message 0 = Receive Buffer 0 has not received a new message Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 WAKIF R/W-0 ERRIF R/W-0 TXB2IF R/W-0 TXB1IF R/W-0 TXB0IF R/W-0 RXB1IF R/W-0 RXB0IF bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 206 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 17-34: PIE3 - PERIPHERAL INTERRUPT ENABLE REGISTER R/W-0 IRXIE bit 7 bit 7 IRXIE: CAN Invalid Received Message Interrupt Enable bit 1 = Enable invalid message received interrupt 0 = Disable invalid message received interrupt WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit 1 = Enable bus activity wake-up interrupt 0 = Disable bus activity wake-up interrupt ERRIE: CAN Bus Error Interrupt Enable bit 1 = Enable CAN bus error interrupt 0 = Disable CAN bus error interrupt TXB2IE: CAN Transmit Buffer 2 Interrupt Enable bit 1 = Enable Transmit Buffer 2 interrupt 0 = Disable Transmit Buffer 2 interrupt TXB1IE: CAN Transmit Buffer 1 Interrupt Enable bit 1 = Enable Transmit Buffer 1 interrupt 0 = Disable Transmit Buffer 1 interrupt TXB0IE: CAN Transmit Buffer 0 Interrupt Enable bit 1 = Enable Transmit Buffer 0 interrupt 0 = Disable Transmit Buffer 0 interrupt RXB1IE: CAN Receive Buffer 1 Interrupt Enable bit 1 = Enable Receive Buffer 1 interrupt 0 = Disable Receive Buffer 1 interrupt RXB0IE: CAN Receive Buffer 0 Interrupt Enable bit 1 = Enable Receive Buffer 0 interrupt 0 = Disable Receive Buffer 0 interrupt Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 WAKIE R/W-0 ERRIE R/W-0 TXB2IE R/W-0 TXB1IE R/W-0 TXB0IE R/W-0 RXB1IE R/W-0 RXB0IE bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 207 PIC18CXX8 REGISTER 17-35: IPR3 - PERIPHERAL INTERRUPT PRIORITY REGISTER R/W-0 IRXIP bit 7 bit 7 IRXIP: CAN Invalid Received Message Interrupt Priority bit 1 = High priority 0 = Low priority WAKIP: CAN Bus Activity Wake-up Interrupt Priority bit 1 = High priority 0 = Low priority ERRIP: CAN bus Error Interrupt Priority bit 1 = High priority 0 = Low priority TXB2IP: CAN Transmit Buffer 2 Interrupt Priority bit 1 = High priority 0 = Low priority TXB1IP: CAN Transmit Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority TXB0IP: CAN Transmit Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority RXB1IP: CAN Receive Buffer 1 Interrupt Priority bit 1 = High priority 0 = Low priority RXB0IP: CAN Receive Buffer 0 Interrupt Priority bit 1 = High priority 0 = Low priority Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown R/W-0 WAKIP R/W-0 ERRIP R/W-0 TXB2IP R/W-0 TXB1IP R/W-0 TXB0IP R/W-0 RXB1IP R/W-0 RXB0IP bit 0 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS30475A-page 208 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 17-1: Address F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h Note: CAN CONTROLLER REGISTER MAP Name Address F5Fh F5Eh F5Dh F5Ch F5Bh F5Ah F59h F58h F57h F56h F55h F54h F53h F52h F51h F50h F4Fh F4Eh F4Dh F4Ch F4Bh F4Ah F49h F48h F47h F46h F45h F44h F43h F42h F41h F40h Name CANSTAT RXB1D7 RXB1D6 RXB1D5 RXB1D4 RXB1D3 RXB1D2 RXB1D1 RXB1D0 RXB1DLC RXB1EIDL RXB1EIDH RXB1SIDL RXB1SIDH RXB1CON CANSTAT TXB0D7 TXB0D6 TXB0D5 TXB0D4 TXB0D3 TXB0D2 TXB0D1 TXB0D0 TXB0DLC TXB0EIDL TXB0EIDH TXB0SIDL TXB0SIDH TXB0CON Address F3Fh F3Eh F3Dh F3Ch F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F2Fh F2Eh F2Dh F2Ch F2Bh F2Ah F29h F28h F27h F26h F25h F24h F23h F22h F21h F20h Name CANSTAT TXB1D7 TXB1D6 TXB1D5 TXB1D4 TXB1D3 TXB1D2 TXB1D1 TXB1D0 TXB1DLC TXB1EIDL TXB1EIDH TXB1SIDL TXB1SIDH TXB1CON CANSTAT TXB2D7 TXB2D6 TXB2D5 TXB2D4 TXB2D3 TXB2D2 TXB2D1 TXB2D0 TXB2DLC TXB2EIDL TXB2EIDH TXB2SIDL TXB2SIDH TXB2CON Address F1Fh F1Eh F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah F09h F08h F07h F06h F05h F04h F03h F02h F01h F00h Name RXM1EIDL RXM1EIDH RXM1SIDL RXM1SIDH RXM0EIDL RXM0EIDH RXM0SIDL RXM0SIDH RXF5EIDL RXF5EIDH RXF5SIDL RXF5SIDH RXF4EIDL RXF4EIDH RXF4SIDL RXF4SIDH RXF3EIDL RXF3EIDH RXF3SIDL RXF3SIDH RXF2EIDL RXF2EIDH RXF2SIDL RXF2SIDH RXF1EIDL RXF1EIDH RXF1SIDL RXF1SIDH RXF0EIDH RXF0EIDL RXF0SIDL RXF0SIDH TXERRCNT RXERRCNT COMSTAT CIOCON BRGCON3 BRGCON2 BRGCON1 CANCON CANSTAT RXB0D7 RXB0D6 RXB0D5 RXB0D4 RXB0D3 RXB0D2 RXB0D1 RXB0D0 RXB0DLC RXB0EIDL RXB0EIDH RXB0SIDL RXB0SIDH RXB0CON Shaded registers are available in Access Bank Low area while the rest are available in Bank 15. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 209 PIC18CXX8 17.3 CAN Modes of Operation 17.3.2 DISABLE MODE The PIC18CXX8 has the following modes of operation. These modes are: * * * * * * Configuration mode Disable mode Normal Operation mode Listen Only mode Loopback mode Error Recognition mode (selected through CANRXM bits) In Disable mode, the module will not transmit or receive. The module has the ability to set the WAKIF bit due to bus activity, however, any pending interrupts will remain and the error counters will retain their value. If REQOP<2:0> is set to 001, the module will enter the module Disable mode. This mode is similar to disabling other peripheral modules by turning off the module enables. This causes the module internal clock to stop unless the module is active (i.e., receiving or transmitting a message). If the module is active, the module will wait for 11 recessive bits on the CAN bus, detect that condition as an idle bus, then accept the module disable command. OPMODE<2:0>=001 indicates whether the module successfully went into module Disable mode The WAKIF interrupt is the only module interrupt that is still active in the module Disable mode. If the WAKIE is set, the processor will receive an interrupt whenever the CAN bus detects a dominant state, as occurs with a SOF. The I/O pins will revert to normal I/O function when the module is in the module Disable mode. 17.3.3 NORMAL MODE Modes are requested by setting the REQOP bits, except the Error Recognition mode, which is requested through the CANRXM bits. Entry into a mode is acknowledged by monitoring the OPMODE bits. When changing modes, the mode will not actually change until all pending message transmissions are complete. Because of this, the user must verify that the device has actually changed into the requested mode before further operations are executed. 17.3.1 CONFIGURATION MODE The CAN module has to be initialized before the activation. This is only possible if the module is in the Configuration mode. The Configuration mode is requested by setting REQOP2 bit. Only when the status bit OPMODE2 has a high level, the initialization can be performed. Afterwards, the configuration registers and the acceptance mask registers and the acceptance filter registers can be written. The module is activated by setting the control bits CFGREQ to zero. The module will protect the user from accidentally violating the CAN protocol through programming errors. All registers which control the configuration of the module can not be modified while the module is on-line. The CAN module will not be allowed to enter the Configuration mode while a transmission is taking place. The CONFIG bit serves as a lock to protect the following registers. * * * * Configuration registers Bus Timing registers Identifier Acceptance Filter registers Identifier Acceptance Mask registers This is the standard operating mode of the PIC18CXX8. In this mode, the device actively monitors all bus messages and generates acknowledge bits, error frames, etc. This is also the only mode in which the PIC18CXX8 will transmit messages over the CAN bus. 17.3.4 LISTEN ONLY MODE In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to configuration registers that are access restricted in other modes. Listen Only mode provides a means for the PIC18CXX8 to receive all messages, including messages with errors. This mode can be used for bus monitor applications, or for detecting the baud rate in `hot plugging' situations. For auto-baud detection, it is necessary that there are at least two other nodes which are communicating with each other. The baud rate can be detected empirically by testing different values until valid messages are received. The Listen Only mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or acknowledge signals. The filters and masks can be used to allow only particular messages to be loaded into the receive registers, or the filter masks can be set to all zeros to allow a message with any identifier to pass. The error counters are reset and deactivated in this state. The Listen Only mode is activated by setting the mode request bits in the CANCON register. DS30475A-page 210 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.3.5 LOOPBACK MODE 17.4.2 TRANSMIT PRIORITY This mode will allow internal transmission of messages from the transmit buffers to the receive buffers, without actually transmitting messages on the CAN bus. This mode can be used in system development and testing. In this mode, the ACK bit is ignored and the device will allow incoming messages from itself just as if they were coming from another node. The Loopback mode is a silent mode, meaning no messages will be transmitted while in this state, including error flags or acknowledge signals. The TXCAN pin will revert to port I/O while the device is in this mode. The filters and masks can be used to allow only particular messages to be loaded into the receive registers. The masks can be set to all zeros to provide a mode that accepts all messages. The Loopback mode is activated by setting the mode request bits in the CANCON register. 17.3.6 ERROR RECOGNITION MODE Transmit priority is a prioritization, within the PIC18CXX8, of the pending transmittable messages. This is independent from, and not related to, any prioritization implicit in the message arbitration scheme built into the CAN protocol. Prior to sending the SOF, the priority of all buffers that are queued for transmission is compared. The transmit buffer with the highest priority will be sent first. If two buffers have the same priority setting, the buffer with the highest buffer number will be sent first. There are four levels of transmit priority. If TXP bits for a particular message buffer are set to 11, that buffer has the highest possible priority. If TXP bits for a particular message buffer are 00, that buffer has the lowest possible priority. 17.4.3 INITIATING TRANSMISSION To initiate message transmission, the TXREQ bit must be set for each buffer to be transmitted. When TXREQ is set, the TXABT, TXLARB and TXERR bits will be cleared. Setting the TXREQ bit does not initiate a message transmission, it merely flags a message buffer as ready for transmission. Transmission will start when the device detects that the bus is available. The device will then begin transmission of the highest priority message that is ready. When the transmission has completed successfully, the TXREQ bit will be cleared, the TXBnIF bit will be set, and an interrupt will be generated if the TXBnIE bit is set. If the message transmission fails, the TXREQ will remain set indicating that the message is still pending for transmission and one of the following condition flags will be set. If the message started to transmit but encountered an error condition, the TXERR and the IRXIF bits will be set and an interrupt will be generated. If the message lost arbitration, the TXLARB bit will be set. 17.4.4 ABORTING TRANSMISSION The module can be set to ignore all errors and receive any message. The Error Recognition mode is activated by setting the RXM<1:0> bits in the RXBnCON registers to 11. In this mode, the data which is in the message assembly buffer until the error time, is copied in the receive buffer and can be read via the CPU interface. In addition, the data which was on the internal sampling of the CAN bus at the error time and the state vector of the protocol state machine and the bit counter CntCan, are stored in registers and can be read. 17.4 17.4.1 CAN Message Transmission TRANSMIT BUFFERS The PIC18CXX8 implements three Transmit Buffers. Each of these buffers occupies 14 bytes of SRAM and are mapped into the device memory maps. For the MCU to have write access to the message buffer, the TXREQ bit must be clear, indicating that the message buffer is clear of any pending message to be transmitted. At a minimum, the TXBNSIDH, TXBNSIDL, and TXBNDLC registers must be loaded. If data bytes are present in the message, the TXBNDm registers must also be loaded. If the message is to use extended identifiers, the TXBNEIDm registers must also be loaded and the EXIDE bit set. Prior to sending the message, the MCU must initialize the TXINE bit to enable or disable the generation of an interrupt when the message is sent. The MCU must also initialize the TXP priority bits (see Section 17.4.2). The MCU can request to abort a message by clearing the TXBnCON.TXREQ bit associated with the corresponding message buffer. Setting CANCON.ABAT bit will request an abort of all pending messages. If the message has not yet started transmission, or if the message started but is interrupted by loss of arbitration or an error, the abort will be processed. The abort is indicated when the module sets TXBnCON.ABTF bits. If the message has started to transmit, it will attempt to transmit the current message fully. If the current message is transmitted fully and is not lost to arbitration or an error, the ABTF bit will not be set, because the message was transmitted successfully. Likewise, if a message is being transmitted during an abort request and the message is lost to arbitration or an error, the message will not be re-transmitted and the ABTF bit will be set, indicating that the message was successfully aborted. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 211 PIC18CXX8 FIGURE 17-2: TRANSMIT MESSAGE FLOWCHART Start The message transmission sequence begins when the device determines that the TXREQ for any of the transmit registers has been set. No Are any TXREQ bits = 1 ? Yes Clear: TXABT, TXLARB, and TXERR Clearing the TXREQ bit while it is set, or setting the ABAT bit before the message has started transmission will abort the message. Is CAN bus available to start transmission ? Yes No Is TXREQ = 0 ABAT = 1 ? Yes No Examine TXPRI <1:0> to Determine Highest Priority Message Begin transmission (SOF) Was Message Transmitted Successfully? No Set TXERR = 1 Yes Set TXREQ = 0 Is TXLARB = 1? Yes Generate Interrupt Is TXIE = 1? No A message can also be aborted if a message error or lost arbitration condition occurred during transmission. Yes Arbitration lost during transmission Set TXBUFE = 1 The TXIE bit determines if an interrupt should be generated when a message is successfully transmitted. is TXREQ = 0 or TXABT = 1 ? No Yes Abort Transmission: Set TXABT = 1 END DS30475A-page 212 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.5 17.5.1 Message Reception RECEIVE MESSAGE BUFFERING 17.5.3 RECEIVE PRIORITY The PIC18CXX8 includes two full receive buffers with multiple acceptance filters for each. There is also a separate Message Assembly Buffer (MAB), which acts as a third receive buffer (see Figure 17-3). 17.5.2 RECEIVE BUFFERS Of the three receive buffers, the MAB is always committed to receiving the next message from the bus. The remaining two receive buffers are called RXB0 and RXB1 and can receive a complete message from the protocol engine. The MCU can access one buffer while the other buffer is available for message reception, or holding a previously received message. The MAB assembles all messages received. These messages will be transferred to the RXBN buffers, only if the acceptance filter criteria are met. Note: The entire contents of the MAB is moved into the receive buffer once a message is accepted. This means that regardless of the type of identifier (standard or extended) and the number of data bytes received, the entire receive buffer is overwritten with the MAB contents. Therefore, the contents of all registers in the buffer must be assumed to have been modified when any message is received. When a message is moved into either of the receive buffers, the appropriate RXBnIF bit is set. This bit must be cleared by the MCU when it has completed processing the message in the buffer, in order to allow a new message to be received into the buffer. This bit provides a positive lockout to ensure that the MCU has finished with the message before the PIC18CXX8 attempts to load a new message into the receive buffer. If the RXBnIE bit is set, an interrupt will be generated to indicate that a valid message has been received. RXB0 is the higher priority buffer and has two message acceptance filters associated with it. RXB1 is the lower priority buffer and has four acceptance filters associated with it. The lower number of acceptance filters makes the match on RXB0 more restrictive and implies a higher priority for that buffer. Additionally, the RXB0CON register can be configured such that if RXB0 contains a valid message, and another valid message is received, an overflow error will not occur and the new message will be moved into RXB1, regardless of the acceptance criteria of RXB1. There are also two programmable acceptance filter masks available, one for each receive buffer (see Section 4.5). When a message is received, bits <3:0> of the RXBNCON register will indicate the acceptance filter number that enabled reception, and whether the received message is a remote transfer request. The RXM bits set special receive modes. Normally, these bits are set to 00 to enable reception of all valid messages, as determined by the appropriate acceptance filters. In this case, the determination of whether or not to receive standard or extended messages is determined by the EXIDE bit in the acceptance filter register. If the RXM bits are set to 01 or 10, the receiver will accept only messages with standard or extended identifiers, respectively. If an acceptance filter has the EXIDE bit set such that it does not correspond with the RXM mode, that acceptance filter is rendered useless. These two modes of RXM bits can be used in systems where it is known that only standard or extended messages will be on the bus. If the RXM bits are set to 11, the buffer will receive all messages, regardless of the values of the acceptance filters. Also, if a message has an error before the end of frame, that portion of the message assembled in the MAB before the error frame, will be loaded into the buffer. This mode has some value in debugging a CAN system and would not be used in an actual system environment. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 213 PIC18CXX8 FIGURE 17-3: RECEIVE BUFFER BLOCK DIAGRAM Acceptance Mask RXM1 Acceptance Filter RXF2 Acceptance Mask RXM0 Acceptance Filter RXF3 A c c e p t Acceptance Filter RXF0 A c c e p t Acceptance Filter RXF4 Acceptance Filter RXF1 Acceptance Filter RXF5 R X B 0 Identifier M A B Identifier R X B 1 Data Field Data Field DS30475A-page 214 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 17-4: MESSAGE RECEPTION FLOWCHART Start No Detect Start of Message? Yes Begin Loading Message into Message Assembly Buffer (MAB) Generate Error Frame No Valid Message Received? Yes Yes, meets criteria Yes, meets criteria Message for RXB1 for RXBO Identifier meets a filter criteria? No Go to Start The RXRDY bit determines if the receive register is empty and able to accept a new message. The RXB0DBEN bit determines if RXB0 can roll over into RXB1 if it is full. Is RXRDY = 0? No Is RX0DBEN = 1? Yes Yes Move message into RXB0 No Generate Overrun Error: Set RXB0OVFL Generate Overrun Error: Set RXB1OVFL No Is RXRDY = 0? Set RXRDY = 1 No Yes Move message into RXB1 Is ERRIE = 1? Yes Go to Start Set FILHIT <2:0> according to which filter criteria was met Set FILHIT <0> according to which filter criteria was met Set RXRDY = 1 Is RXIE = 1? Yes No Generate Interrupt Set CANSTAT <3:0> according to which receive buffer the message was loaded into Yes Is RXIE = 1? No 2000 Microchip Technology Inc. Advanced Information DS30475A-page 215 PIC18CXX8 17.6 Message Acceptance Filters and Masks The coding of the RXB0DBEN bit enables these three bits to be used similarly to the FILHIT bits and to distinguish a hit on filter RXF0 and RXF1, in either RXB0, or after a roll over into RXB1. * * * * 111 = Acceptance Filter 1 (RXF1) 110 = Acceptance Filter 0 (RXF0) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 The Message Acceptance Filters and Masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers. Once a valid message has been received into the MAB, the identifier fields of the message are compared to the filter values. If there is a match, that message will be loaded into the appropriate receive buffer. The filter masks are used to determine which bits in the identifier are examined with the filters. A truth table is shown below in Table 17-2 that indicates how each bit in the identifier is compared to the masks and filters to determine if a the message should be loaded into a receive buffer. The mask essentially determines which bits to apply the acceptance filters to. If any mask bit is set to a zero, then that bit will automatically be accepted, regardless of the filter bit. If the RXB0DBEN bit is clear, there are six codes corresponding to the six filters. If the RXB0DBEN bit is set, there are six codes corresponding to the six filters, plus two additional codes corresponding to RXF0 and RXF1 filters that roll over into RXB1. If more than one acceptance filter matches, the FILHIT bits will encode the binary value of the lowest numbered filter that matched. In other words, if filter RXF2 and filter RXF4 match, FILHIT will be loaded with the value for RXF2. This essentially prioritizes the acceptance filters with a lower number filter having higher priority. Messages are compared to filters in ascending order of filter number. The mask and filter registers can only be modified when the PIC18CXX8 is in Configuration mode. The mask and filter registers cannot be read outside of Configuration mode. When outside of Configuration mode, all mask and filter registers will be read as `0'. TABLE 17-2: Mask bit n 0 1 1 1 1 FILTER/MASK TRUTH TABLE Message Identifier bit n001 X 0 1 0 1 Accept or Reject bit n Accept Accept Reject Reject Accept Filter bit n X 0 0 1 1 Legend: X = don't care As shown in the Receive Buffers Block Diagram (Figure 17-3), acceptance filters RXF0 and RXF1, and filter mask RXM0 are associated with RXB0. Filters RXF2, RXF3, RXF4, and RXF5 and mask RXM1 are associated with RXB1. When a filter matches and a message is loaded into the receive buffer, the filter number that enabled the message reception is loaded into the FILHIT bit(s). For RXB1, the RXB1CON register contains the FILHIT<2:0> bits. They are coded as follows: * * * * * * 101 = Acceptance Filter 5 (RXF5) 100 = Acceptance Filter 4 (RXF4) 011 = Acceptance Filter 3 (RXF3) 010 = Acceptance Filter 2 (RXF2) 001 = Acceptance Filter 1 (RXF1) 000 = Acceptance Filter 0 (RXF0) Note: 000 and 001 can only occur if the RXB0DBEN bit is set in the RXB0CON register, allowing RXB0 messages to roll over into RXB1. DS30475A-page 216 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 17-5: MESSAGE ACCEPTANCE MASK AND FILTER OPERATION Acceptance Filter Register RXFn0 RXMn0 Acceptance Mask Register RXFn1 RXMn1 RxRqst RXFnn RXMnn Message Assembly Buffer Identifier 2000 Microchip Technology Inc. Advanced Information DS30475A-page 217 PIC18CXX8 17.7 Baud Rate Setting All nodes on a given CAN bus must have the same nominal bit rate. The CAN protocol uses Non-Return-to-Zero (NRZ) coding, which does not encode a clock within the data stream. Therefore, the receive clock must be recovered by the receiving nodes and synchronized to the transmitters clock. As oscillators and transmission time may vary from node to node, the receiver must have some type of Phase Lock Loop (PLL) synchronized to data transmission edges, to synchronize and maintain the receiver clock. Since the data is NRZ coded, it is necessary to include bit stuffing to ensure that an edge occurs at least every six bit times, to maintain the Digital Phase Lock Loop (DPLL) synchronization. The bit timing of the PIC18CXX8 is implemented using a DPLL that is configured to synchronize to the incoming data, and provide the nominal timing for the transmitted data. The DPLL breaks each bit time into multiple segments, made up of minimal periods of time called the time quanta (TQ). Bus timing functions executed within the bit time frame, such as synchronization to the local oscillator, network transmission delay compensation, and sample point positioning, are defined by the programmable bit timing logic of the DPLL. All devices on the CAN bus must use the same bit rate. However, all devices are not required to have the same master oscillator clock frequency. For the different clock frequencies of the individual devices, the bit rate has to be adjusted by appropriately setting the baud rate prescaler and number of time quanta in each segment. The nominal bit rate is the number of bits transmitted per second assuming an ideal transmitter with an ideal oscillator, in the absence of resynchronization. The nominal bit rate is defined to be a maximum of 1Mb/s. Nominal Bit Time is defined as: TBIT = 1 / NOMlNAL BlT RATE The nominal bit time can be thought of as being divided into separate non-overlapping time segments. These segments are shown in Figure 17-6. * * * * Synchronization Segment (Sync_Seg) Propagation Time Segment (Prop_Seg) Phase Buffer Segment 1 (Phase_Seg1) Phase Buffer Segment 2 [Phase_Seg2) Nominal Bit Time = TQ * (Sync_Seg + Prop_Seg + Phase_Seg1 + Phase_Seg2) The time segments and also, the nominal bit time, are made up of integer units of time called time quanta or TQ (see Figure 17-6). By definition, the nominal bit time is programmable from a minimum of 8 TQ to a maximum of 25 TQ. Also by definition, the minimum nominal bit time is 1 s, corresponding to a maximum 1 Mb/s rate. FIGURE 17-6: BIT TIME PARTITIONING Input Signal Sync Prop Segment Phase Segment 1 Sample Point Phase Segment 2 TQ DS30475A-page 218 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.7.1 TIME QUANTA 17.7.4 PHASE BUFFER SEGMENTS The Time Quanta is a fixed unit of time derived from the oscillator period. There is a programmable baud rate prescaler, with integral values ranging from 1 to 64, in addition to a fixed divide by two for clock generation. The Phase Buffer Segments are used to optimally locate the sampling point of the received bit, within the nominal bit time. The sampling point occurs between phase segment 1 and phase segment 2. These segments can be lengthened or shortened by the resynchronization process. The end of phase segment 1 determines the sampling point within a bit time. Phase segment 1 is programmable from 1 TQ to 8 TQ in duration. Phase segment 2 provides delay before the next transmitted data transition and is also programmable from 1 TQ to 8 TQ in duration (however, due to IPT requirements the actual minimum length of phase segment 2 is 2 TQ, or it may be defined to be equal to the greater of phase segment 1 or the Information Processing Time (IPT) ). 17.7.5 SAMPLE POINT EXAMPLE 17-2: CALCULATION FOR FOSC = 16MHz If Fosc = 16 MHz, BRP<5:0> = 00h, and Nominal Bit Time = 8 TQ; then TQ = 125 nsec and Nominal Bit Rate = 1 Mb/s EXAMPLE 17-3: CALCULATION FOR FOSC = 20MHz If FOSC = 20 MHz, BRP<5:0> = 01h, and Nominal Bit Time = 8 TQ; then TQ = 200nsec and Nominal Bit Rate = 625 Kb/s EXAMPLE 17-4: CALCULATION FOR FOSC = 25MHz If Fosc = 25 MHz, BRP<5:0> = 3Fh, and Nominal Bit Time = 25 TQ; then TQ = 5.12 usec and Nominal Bit Rate = 7.8 Kb/s The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system-wide specified nominal bit time. This means that all oscillators must have a TOSC that is a integral divisor of TQ. It should also be noted that although the number of TQ is programmable from 4 to 25, the usable minimum is 8 TQ. A bit time of less than 8 TQ in length is not guaranteed to operate correctly. 17.7.2 SYNCHRONIZATION SEGMENT The Sample Point is the point of time at which the bus level is read and value of the received bit is determined. The sampling point occurs at the end of phase segment 1. If the bit timing is slow and contains many TQ, it is possible to specify multiple sampling of the bus line at the sample point. The value of the received bit is determined to be the value of the majority decision of three values. The three samples are taken at the sample point, and twice before with a time of TQ/2 between each sample. 17.7.6 INFORMATION PROCESSING TIME The Information Processing Time (IPT) is the time segment, starting at the sample point, that is reserved for calculation of the subsequent bit level. The CAN specification defines this time to be less than or equal to 2 TQ. The PIC18CXX8 defines this time to be 2 TQ. Thus, phase segment 2 must be at least 2 TQ long. This part of the bit time is used to synchronize the various CAN nodes on the bus. The edge of the input signal is expected to occur during the sync segment. The duration is 1 TQ. 17.7.3 PROPAGATION SEGMENT This part of the bit time is used to compensate for physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes. The length of the Propagation Segment can be programmed from 1 TQ to 8 TQ by setting the PRSEG2:PRSEG0 bits. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 219 PIC18CXX8 17.8 Synchronization To compensate for phase shifts between the oscillator frequencies of each of the nodes on the bus, each CAN controller must be able to synchronize to the relevant signal edge of the incoming signal. When an edge in the transmitted data is detected, the logic will compare the location of the edge to the expected time (Sync Seg). The circuit will then adjust the values of phase segment 1 and phase segment 2, as necessary. There are two mechanisms used for synchronization. 17.8.1 HARD SYNCHRONIZATION The phase error of an edge is given by the position of the edge relative to Sync Seg, measured in TQ. The phase error is defined in magnitude of TQ as follows: * e = 0 if the edge lies within SYNCESEG. * e > 0 if the edge lies before the SAMPLE POINT. * e < 0 if the edge lies after the SAMPLE POINT of the previous bit. If the magnitude of the phase error is less than, or equal to, the programmed value of the synchronization jump width, the effect of a resynchronization is the same as that of a hard synchronization. If the magnitude of the phase error is larger than the synchronization jump width, and if the phase error is positive, then phase segment 1 is lengthened by an amount equal to the synchronization jump width. If the magnitude of the phase error is larger than the resynchronization jump width, and if the phase error is negative, then phase segment 2 is shortened by an amount equal to the synchronization jump width. 17.8.3 SYNCHRONIZATION RULES Hard Synchronization is only done when there is a recessive to dominant edge during a BUS IDLE condition, indicating the start of a message. After hard synchronization, the bit time counters are restarted with Sync Seg. Hard synchronization forces the edge, which has occurred to lie within the synchronization segment of the restarted bit time. Due to the rules of synchronization, if a hard synchronization occurs, there will not be a resynchronization within that bit time. 17.8.2 RESYNCHRONIZATION As a result of Resynchronization, phase segment 1 may be lengthened, or phase segment 2 may be shortened. The amount of lengthening or shortening of the phase buffer segments has an upper bound given by the Synchronization Jump Width (SJW). The value of the SJW will be added to phase segment 1 (see Figure 17-7), or subtracted from phase segment 2 (see Figure 17-8). The SJW is programmable between 1 TQ and 4 TQ. Clocking information will only be derived from recessive to dominant transitions. The property that only a fixed maximum number of successive bits have the same value, ensures resynchronization to the bit stream during a frame. * Only one synchronization within one bit time is allowed. * An edge will be used for synchronization only if the value detected at the previous sample point (previously read bus value) differs from the bus value immediately after the edge. * All other recessive to dominant edges, fulfilling rules 1 and 2, will be used for resynchronization with the exception that a node transmitting a dominant bit will not perform a resynchronization, as a result of a recessive to dominant edge with a positive phase error. DS30475A-page 220 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 17-7: LENGTHENING A BIT PERIOD Input Signal Sync Prop Segment Phase Segment 1 SJW Phase Segment 2 Sample Point Nominal Bit Length Actual Bit Length TQ FIGURE 17-8: Input Signal SHORTENING A BIT PERIOD Sync Prop Segment Phase Segment 1 Phase Segment 2 SJW Sample Point TQ Actual Bit Length Nominal Bit Length 2000 Microchip Technology Inc. Advanced Information DS30475A-page 221 PIC18CXX8 17.9 Programming Time Segments 17.11 Bit Timing Configuration Registers Some requirements for programming of the time segments: * Prop Seg + Phase Seg 1 Phase Seg 2 * Phase Seg 2 Sync Jump Width For example, assuming that a 125 kHz CAN baud rate with FOSC = 20 MHz is desired: TOSC = 50nsec, choose BRP<5:0> = 04h, then TQ = 500nsec. To obtain 125 kHz, the bit time must be 16 TQ. Sync Seg = 1 TQ; Prop Seg = 2 TQ; So, setting Phase Seg 1 = 7 TQ would place the sample at 10 TQ after the transition. This would leave 6 TQ for Phase Seg 2. Since Phase Seg 2 is 6, by the rules, SJW could be the maximum of 4 TQ. However, normally a large SJW is only necessary when the clock generation of the different nodes is inaccurate or unstable, such as using ceramic resonators. So an SJW of 1 is typically enough. The configuration registers (BRGCON1, BRGCON2, BRGCON3) control the bit timing for the CAN bus interface. These registers can only be modified when the PIC18CXX8 is in Configuration mode. 17.11.1 BRGCON1 The BRP bits control the baud rate prescaler. The SJW<1:0> bits select the synchronization jump width in terms of number of TQ's. 17.11.2 BRGCON2 The PRSEG bits set the length, in TQ's, of the propagation segment. The SEG1PH bits set the length, in TQ's, of phase segment 1. The SAM bit controls how many times the RXCAN pin is sampled. Setting this bit to a `1' causes the bus to be sampled three times; twice at TQ/2 before the sample point, and once at the normal sample point (which is at the end of phase segment 1). The value of the bus is determined to be the value read during at least two of the samples. If the SAM bit is set to a `0', then the RXCAN pin is sampled only once at the sample point. The SEG2PHTS bit controls how the length of phase segment 2 is determined. If this bit is set to a `1', then the length of phase segment 2 is determined by the SEG2PH bits of BRGCON3. If the SEG2PHTS bit is set to a `0', then the length of phase segment 2 is the greater of phase segment 1 and the information processing time (which is fixed at 2 TQ for the PIC18CXX8). 17.11.3 BRGCON3 The PHSEG2<2:0> bits set the length, in TQ's, of phase segment 2, if the SEG2PHTS bit is set to a `1'. If the SEG2PHTS bit is set to a `0', then the PHSEG2<2:0> bits have no effect. 17.10 Oscillator Tolerance The bit timing requirements allow ceramic resonators to be used in applications with transmission rates of up to 125 kbit/sec, as a rule of thumb. For the full bus speed range of the CAN protocol, a quartz oscillator is required. A maximum node-to-node oscillator variation of 1.7% is allowed. DS30475A-page 222 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.12 Error Detection 17.12.6 ERROR STATES Detected errors are made public to all other nodes via error frames. The transmission of the erroneous message is aborted and the frame is repeated as soon as possible. Furthermore, each CAN node is in one of the three error states "error-active", "error-passive" or "bus-off" according to the value of the internal error counters. The error-active state is the usual state, where the bus node can transmit messages and active error frames (made of dominant bits), without any restrictions. In the error-passive state, messages and passive error frames (made of recessive bits) may be transmitted. The bus-off state makes it temporarily impossible for the station to participate in the bus communication. During this state, messages can neither be received nor transmitted. 17.12.7 ERROR MODES AND ERROR COUNTERS The PIC18CXX8 contains two error counters: the Receive Error Counter (RXERRCNT), and the Transmit Error Counter (TXERRCNT). The values of both counters can be read by the MCU. These counters are incremented or decremented in accordance with the CAN bus specification. The PIC18CXX8 is error-active if both error counters are below the error-passive limit of 128. It is error-passive if at least one of the error counters equals or exceeds 128. It goes to bus-off if the transmit error counter equals or exceeds the bus-off limit of 256. The device remains in this state, until the bus-off recovery sequence is received. The bus-off recovery sequence consists of 128 occurrences of 11 consecutive recessive bits (see Figure 17-9). Note that the CAN module, after going bus-off, will recover back to error-active, without any intervention by the MCU, if the bus remains idle for 128 X 11 bit times. If this is not desired, the error interrupt service routine should address this. The current error mode of the CAN module can be read by the MCU via the COMSTAT register. Additionally, there is an error state warning flag bit, EWARN, which is set if at least one of the error counters equals or exceeds the error warning limit of 96. EWARN is reset if both error counters are less than the error warning limit. The CAN protocol provides sophisticated error detection mechanisms. The following errors can be detected. 17.12.1 CRC ERROR With the Cyclic Redundancy Check (CRC), the transmitter calculates special check bits for the bit sequence, from the start of a frame until the end of the data field. This CRC sequence is transmitted in the CRC Field. The receiving node also calculates the CRC sequence using the same formula and performs a comparison to the received sequence. If a mismatch is detected, a CRC error has occurred and an error frame is generated. The message is repeated. 17.12.2 ACKNOWLEDGE ERROR In the acknowledge field of a message, the transmitter checks if the acknowledge slot (which has sent out as a recessive bit) contains a dominant bit. If not, no other node has received the frame correctly. An acknowledge error has occurred; an error frame is generated and the message will have to be repeated. 17.12.3 FORM ERROR lf a node detects a dominant bit in one of the four segments, including end of frame, interframe space, acknowledge delimiter, or CRC delimiter, then a form error has occurred and an error frame is generated. The message is repeated. 17.12.4 BIT ERROR A Bit Error occurs if a transmitter sends a dominant bit and detects a recessive bit, or if it sends a recessive bit and detects a dominant bit, when monitoring the actual bus level and comparing it to the just transmitted bit. In the case where the transmitter sends a recessive bit and a dominant bit is detected during the arbitration field and the acknowledge slot, no bit error is generated because normal arbitration is occurring. 17.12.5 STUFF BIT ERROR lf, between the start of frame and the CRC delimiter, six consecutive bits with the same polarity are detected, the bit stuffing rule has been violated. A Stuff Bit Error occurs and an error frame is generated. The message is repeated. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 223 PIC18CXX8 FIGURE 17-9: ERROR MODES STATE DIAGRAM RESET RXERRCNT < 127 or TXERRCNT < 127 Error Active 128 occurrences of 11 consecutive "recessive" bits RXERRCNT > 127 or TXERRCNT > 127 Error Passive TXERRCNT > 255 Bus Off DS30475A-page 224 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 17.13 CAN Interrupts 17.13.2 TRANSMIT INTERRUPT When the Transmit Interrupt is enabled, an interrupt will be generated when the associated transmit buffer becomes empty and is ready to be loaded with a new message. The TXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU resetting the TXBnIF bit to a `0'. 17.13.3 RECEIVE INTERRUPT When the Receive Interrupt is enabled, an interrupt will be generated when a message has been successfully received and loaded into the associated receive buffer. This interrupt is activated immediately after receiving the EOF field. The RXBnIF bit will be set to indicate the source of the interrupt. The interrupt is cleared by the MCU resetting the RXBnIF bit to a `0'. 17.13.4 MESSAGE ERROR INTERRUPT When an error occurs during transmission or reception of a message, the message error flag IRXIF will be set and, if the IRXIE bit is set, an interrupt will be generated. This is intended to be used to facilitate baud rate determination when used in conjunction with Listen Only mode. 17.13.5 BUS ACTIVITY WAKE-UP INTERRUPT When the PIC18CXX8 is in SLEEP mode and the bus activity wake-up interrupt is enabled, an interrupt will be generated, and the WAKIF bit will be set, when activity is detected on the CAN bus. This interrupt causes the PIC18CXX8 to exit SLEEP mode. The interrupt is reset by the MCU clearing the WAKIF bit. The module has several sources of interrupts. Each of these interrupts can be individually enabled or disabled. The CANINTF register contains interrupt flags. The CANINTE register contains the enables for the 8 main interrupts. A special set of read only bits in the CANSTAT register (ICODE bits) can be used in combination with a jump table for efficient handling of interrupts. All interrupts have one source, with the exception of the Error Interrupt. Any of the Error Interrupt sources can set the Error Interrupt Flag. The source of the Error Interrupt can be determined by reading the Communication Status register COMSTAT. The interrupts can be broken up into two categories: receive and transmit interrupts. The receive related interrupts are: * * * * * * * * * Receive Interrupts Wake-up Interrupt Receiver Overrun Interrupt Receiver Warning Interrupt Receiver Error Passive Interrupt Transmit Interrupts Transmitter Warning Interrupt Transmitter Error Passive Interrupt Bus Off Interrupt The Transmit related interrupts are 17.13.1 INTERRUPT CODE BITS The source of a pending interrupt is indicated in the ICODE (interrupt code) bits. Interrupts are internally prioritized, such that the lower the ICODE value, the higher the interrupt priority. Once the highest priority interrupt condition has been cleared, the code for the next highest priority interrupt that is pending (if any), will be reflected by the ICODE bits (see Table 17-3). Note that only those interrupt sources that have their associated CANINTE enable bit set will be reflected in the ICODE bits. TABLE 17-3: ICODE<2:0> 000 001 010 011 100 101 110 111 ICODE<2:0> DECODE Boolean Expression ERR*WAK*TX0*TX1*TX2*RX0*RX1 ERR ERR*WAK ERR*WAK*TX0 ERR*WAK*TX0*TX1 ERR*WAK*TX0*TX1*TX2 ERR*WAK*TX0*TX1*TX2*RX0 ERR*WAK*TX0*TX1*TX2*RX0*RX1 2000 Microchip Technology Inc. Advanced Information DS30475A-page 225 PIC18CXX8 17.13.6 ERROR INTERRUPT When the error interrupt is enabled, an interrupt is generated if an overflow condition occurs, or if the error state of transmitter or receiver has changed. The Error Flags in COMSTAT will indicate one of the following conditions. 17.13.6.1 Receiver Overflow An overflow condition occurs when the MAB has assembled a valid received message (the message meets the criteria of the acceptance filters) and the receive buffer associated with the filter is not available for loading of a new message. The associated COMSTAT.RXNOVFL bit will be set to indicate the overflow condition. This bit must be cleared by the MCU. 17.13.6.2 Receiver Warning The receive error counter has reached the MCU warning limit of 96. 17.13.6.3 Transmitter Warning The transmit error counter has reached the MCU warning limit of 96. 17.13.6.4 Receiver Bus-Passive The receive error counter has exceeded the error-passive limit of 127 and the device has gone to error-passive state. 17.13.6.5 Transmitter Bus-Passive The transmit error counter has exceeded the errorpassive limit of 127 and the device has gone to errorpassive state. 17.13.6.6 Bus-Off The transmit error counter has exceeded 255 and the device has gone to bus-off state. 17.13.7 INTERRUPT ACKNOWLEDGE Interrupts are directly associated with one or more status flags in the PIF register. Interrupts are pending as long as one of the flags is set. Once an interrupt flag is set by the device, the flag can not be reset by the MCU until the interrupt condition is removed. DS30475A-page 226 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 18.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has five registers: * * * * * A/D Result High Register (ADRESH) A/D Result Low Register (ADRESL) A/D Control Register 0 (ADCON0) A/D Control Register 1 (ADCON1) A/D Control Register 2 (ADCON2) The analog-to-digital (A/D) converter module has twelve inputs for the PIC18C658 devices and sixteen for the PIC18C858 devices. This module has the ADCON0, ADCON1, and ADCON2 registers. The A/D allows conversion of an analog input signal to a corresponding 10-bit digital number. The ADCON0 register, shown in Register 18-1, controls the operation of the A/D module. The ADCON1 register, shown in Register 18-2, configures the functions of the port pins. The ADCON2, shown in Register 16-3, configures the A/D clock source and justification. REGISTER 18-1: ADCON0 REGISTER U-0 -- bit 7 U-0 -- R/W-0 CHS3 R/W-0 CHS2 R/W-0 CHS1 R/W-0 CHS0 R/W-0 GO/DONE R/W-0 ADON bit 0 bit 7-6 bit 5-2 Unimplemented: Read as '0' CHS3:CHS0: Analog Channel Select bits 0000 = channel 00, (AN0) 0001 = channel 01, (AN1) 0010 = channel 02, (AN2) 0011 = channel 03, (AN3) 0100 = channel 04, (AN4) 0101 = channel 05, (AN5) 0110 = channel 06, (AN6) 0111 = channel 07, (AN7) 1000 = channel 08, (AN8) 1001 = channel 09, (AN9) 1010 = channel 10, (AN10) 1011 = channel 11, (AN11) 1100 = channel 12, (AN12)(1) 1101 = channel 13, (AN13)(1) 1110 = channel 14, (AN14)(1) 1111 = channel 15, (AN15)(1) Note 1: These channels are not available on the PIC18C658 devices. bit 1 GO/DONE: A/D Conversion Status bit When ADON = 1 1 = A/D conversion in progress. Setting this bit starts an A/D conversion cycle. This bit is automatically cleared by hardware when the A/D conversion is complete. 0 = A/D conversion not in progress ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shut off and consumes no operating current Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 227 PIC18CXX8 REGISTER 18-2: U-0 -- bit 7 bit 7-6 bit 5-4 Unimplemented: Read as '0' VCFG1:VCFG0: Voltage Reference Configuration bits ADCON1 REGISTER U-0 -- R/W-0 VCFG1 R/W-0 VCFG0 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 R/W-0 PCFG0 bit 0 A/D VREF+ 00 01 10 11 bit 3:0 AVDD External VREF+ AVDD External VREF+ A/D VREFAVSS AVSS External VREFExternal VREF- PCFG3:PCFG0: A/D Port Configuration Control bits AN15 AN14 AN13 AN12 AN11 AN10 AN9 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A D D D D D D D D D D D D D D D A D D D D D D D D D D D D D D D A A D D D D D D D D D D D D D D A A A D D D D D D D D D D D D D A A A A D D D D D D D D D D D D A A A A A D D D D D D D D D D D A A A A A A D D D D D D D D D D AN8 A A A A A A A D D D D D D D D D AN7 A A A A A A A A D D D D D D D D AN6 A A A A A A A A A D D D D D D D AN5 A A A A A A A A A A D D D D D D AN4 A A A A A A A A A A A D D D D D AN3 AN2 AN1 AN0 A A A A A A A A A A A A D D D D A A A A A A A A A A A A A D D D A A A A A A A A A A A A A A D D A A A A A A A A A A A A A A A D A = Analog input D = Digital I/O Shaded cells = additional A/D channels available on the PIC18C858 devices. Legend: R = Readable bit - n = Value at POR Note: W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown Channels AN15 through AN12 are not available on the 68-pin devices. DS30475A-page 228 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 18-3: ADCON2 REGISTER R/W-0 ADFM bit 7 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified 0 = Left justified Unimplemented: Read as '0' ADCS1:ADCS0: A/D Conversion Clock Select bits 000 = FOSC/2 001 = FOSC/8 010 = FOSC/32 011 = FRC (clock derived from an RC oscillator = 1 MHz max) 100 = FOSC/4 101 = FOSC/16 110 = FOSC/64 111 = FRC (clock derived from an RC oscillator = 1 MHz max) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 ADCS2 R/W-0 ADCS1 R/W-0 ADCS0 bit 0 bit 6-3 bit 2-0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 229 PIC18CXX8 The analog reference voltage is software selectable to either the device's positive and negative supply voltage (VDD and VSS), or the voltage level on the RA3/AN3/VREF+ pin and RA2/AN2/VREF-. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode. To operate in SLEEP, the A/D conversion clock must be derived from the A/D's internal RC oscillator. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. A device RESET forces all registers to their RESET state. This forces the A/D module to be turned off and any conversion is aborted. Each port pin associated with the A/D converter can be configured as an analog input (RA3 can also be a voltage reference), or as a digital I/O. The ADRESH and ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the ADRESH/ADRESL registers, the GO/DONE bit (ADCON0 register) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 18-1. FIGURE 18-1: A/D BLOCK DIAGRAM CHS3:CHS0 1111 1110 1101 1100 1011 1010 1001 1000 0111 0110 0101 0100 VAIN 10-bit Converter A/D (Input Voltage) 0011 0010 VCFG1:VCFG0 VDD VREF+ Reference Voltage VREF0001 0000 AN15 (1) AN14 (1) AN13 (1) AN12 (1) AN11 AN10 AN9 AN8 AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 VSS Note 1: Channels AN15 through AN12 are not available on the PIC18C658. 2: I/O pins have diode protection to VDD and VSS. DS30475A-page 230 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 The value in the ADRESH/ADRESL registers is not modified for a Power-on Reset. The ADRESH/ADRESL registers will contain unknown data after a Power-on Reset. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started. The analog input channels must have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 18.1. After this acquisition time has elapsed, the A/D conversion can be started. The following steps should be followed to do an A/D conversion: 1. Configure the A/D module: * Configure analog pins, voltage reference and digital I/O (ADCON1) * Select A/D input channel (ADCON0) * Select A/D conversion clock (ADCON2) * Turn on A/D module (ADCON0) 2. Configure A/D interrupt (if desired): * Clear ADIF bit * Set ADIE bit * Set GIE bit Wait the required acquisition time. Start conversion: * Set GO/DONE bit (ADCON0 register) Wait for A/D conversion to complete, by either: * Polling for the GO/DONE bit to be cleared OR 6. 7. * Waiting for the A/D interrupt Read A/D Result registers (ADRESH:ADRESL); clear bit ADIF, if required. For next conversion, go to step 1 or step 2, as required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is required before next acquisition starts. 3. 4. 5. FIGURE 18-2: ANALOG INPUT MODEL VDD VT = 0.6 V Rs ANx RIC 1 k Sampling Switch SS RSS VAIN CPIN 5 pF VT = 0.6 V I leakage 500 nA CHOLD = 120 pF VSS Legend: CPIN = input capacitance VT = threshold voltage I LEAKAGE = leakage current at the pin due to various junctions RIC = interconnect resistance SS = sampling switch CHOLD = sample/hold capacitance (from DAC) RSS = sampling switch resistance 6V 5V VDD 4V 3V 2V 5 6 7 8 9 10 11 Sampling Switch ( k ) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 231 PIC18CXX8 18.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 18-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD). The source impedance affects the offset voltage at the analog input (due to pin leakage current). The maximum recommended impedance for analog sources is 2.5k. After the analog input channel is selected (changed), this acquisition must be done before the conversion can be started. Note: When the conversion is started, the holding capacitor is disconnected from the input pin. To calculate the minimum acquisition time, Equation 18-1 may be used. This equation assumes that 1/2 LSb error is used (1024 steps for the A/D). The 1/2 LSb error is the maximum error allowed for the A/D to meet its specified resolution. Example 18-1 shows the calculation of the minimum required acquisition time TACQ. This calculation is based on the following application system assumptions: CHOLD Rs Conversion Error VDD Temperature VHOLD = = = = = 120 pF 2.5 k 1/2 LSb 5V Rss = 7 k 50C (system max.) 0V @ time = 0 EQUATION 18-1: TACQ = ACQUISITION TIME Amplifier Settling Time + Holding Capacitor Charging Time + Temperature Coefficient TAMP + TC + TCOFF = EQUATION 18-2: VHOLD or Tc = = A/D MINIMUM CHARGING TIME (VREF - (VREF/2048)) * (1 - e(-Tc/CHOLD(RIC + RSS + RS))) -(120 pF)(1 k + RSS + RS) ln(1/2047) EXAMPLE 18-1: CALCULATING THE MINIMUM REQUIRED ACQUISITION TIME TACQ = TACQ = TC = TAMP + TC + TCOFF 2 s + Tc + [(Temp - 25C)(0.05 s/C)] -CHOLD (RIC + RSS + RS) ln(1/2047) -120 pF (1 k + 7 k + 2.5 k) ln(0.0004885) -120 pF (10.5 k) ln(0.0004885) -1.26 s (-7.6241) 9.61 s 2 s + 9.61 s + [(50C - 25C)(0.05 s/C)] 11.61 s + 1.25 s 12.86 s Temperature coefficient is only required for temperatures > 25C. TACQ = DS30475A-page 232 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 18.2 Selecting the A/D Conversion Clock 18.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The A/D conversion requires 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selectable. There are seven possible options for TAD: * * * * * * * 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC Internal RC oscillator The ADCON1, TRISA, TRISF and TRISH registers control the operation of the A/D port pins. The port pins needed as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D operation is independent of the state of the CHS3:CHS0 bits and the TRIS bits. Note 1: When reading the port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will convert an analog input. Analog levels on a digitally configured input will not affect the conversion accuracy. 2: Analog levels on any pin defined as a digital input may cause the input buffer to consume current out of the device's specification limits. For correct A/D conversions, the A/D conversion clock (TAD) must be selected to ensure a minimum TAD time of 1.6 s. Table 18-1 shows the resultant TAD times derived from the device operating frequencies and the A/D clock source selected. TABLE 18-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Maximum Device Frequency PIC18CXX8 1.25 MHz 2.50 MHz 5.00 MHz 10.0 MHz 20.0 MHz 40.0 MHz -- PIC18LCXX8(6) 666 kHz 1.33 MHz 2.67 MHz 5.33 MHz 10.67 MHz 21.33 MHz -- ADCS2:ADCS0 000 100 001 101 010 110 x11 Operation 2TOSC 4TOSC 8TOSC 16TOSC 32TOSC 64TOSC RC Note 1: 2: 3: 4: 5: The RC source has a typical TAD time of 4 ms. The RC source has a typical TAD time of 6 ms. These values violate the minimum required TAD time. For faster conversion times, the selection of another clock source is recommended. For device frequencies above 1 MHz, the device must be in SLEEP for the entire conversion or the A/D accuracy may be out of specification. 6: This column is for the LC devices only. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 233 PIC18CXX8 18.4 A/D Conversions 18.5 Use of the CCP2 Trigger Figure 18-3 shows the operation of the A/D converter after the GO bit has been set. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D result register pair will NOT be updated with the partially completed A/D conversion sample. That is, the ADRESH:ADRESL registers will continue to contain the value of the last completed conversion (or the last value written to the ADRESH:ADRESL registers). After the A/D conversion is aborted, a 2TAD wait is required before the next acquisition is started. After this 2TAD wait, acquisition on the selected channel is automatically started. Note: The GO/DONE bit should NOT be set in the same instruction that turns on the A/D. An A/D conversion can be started by the "special event trigger" of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be programmed as 1011 and that the A/D module is enabled (ADON bit is set). When the trigger occurs, the GO/DONE bit will be set, starting the A/D conversion, and the Timer1 (or Timer3) counter will be reset to zero. Timer1 (or Timer3) is reset to automatically repeat the A/D acquisition period with minimal software overhead (moving ADRESH/ADRESL to the desired location). The appropriate analog input channel must be selected and the minimum acquisition done before the "special event trigger" sets the GO/DONE bit (starts a conversion). If the A/D module is not enabled (ADON is cleared), the "special event trigger" will be ignored by the A/D module, but will still reset the Timer1 (or Timer3) counter. FIGURE 18-3: A/D CONVERSION TAD CYCLES Tcy - TAD TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8 TAD9 TAD10 TAD11 b0 b1 b3 b0 b4 b2 b5 b7 b6 b8 b9 Conversion Starts Holding capacitor is disconnected from analog input (typically 100 ns) Set GO bit Next Q4: ADRESH/ADRESL is loaded, GO bit is cleared, ADIF bit is set, holding capacitor is connected to analog input. DS30475A-page 234 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 18-2: Name INTCON PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 ADRESH ADRESL ADCON0 ADCON1 ADCON2 PORTA TRISA PORTF LATF TRISF PORTH(1) LATH (1) SUMMARY OF A/D REGISTERS Bit 6 PEIE/ GIEL ADIF ADIE ADIP CMIF CMIE CMIP Bit 5 TMR0IE RCIF RCIE RCIP -- -- -- Bit 4 INT0IE TXIF TXIE TXIP -- -- -- Bit 3 RBIE SSPIF SSPIE SSPIP BCLIF BCLIE BCLIP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP LVDIF LVDIE LVDIP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3IF TMR3IE TMR3IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP CCP2IF CCP2IE CCP2IP Value on POR, BOR 0000 000x 0000 0000 0000 0000 0000 0000 -0-- 0000 -0-- 0000 -0-- 0000 xxxx xxxx xxxx xxxx CHS3 VCFG1 -- RA5 RF5 LATF5 RH5 LATH5 CHS3 VCFG0 -- RA4 RF4 LATF4 RH4 LATH4 CHS1 PCFG3 -- RA3 RF3 LATF3 RH3 LATH3 CHS0 PCFG2 ADCS2 RA2 RF2 LATF2 RH2 LATH2 GO/DONE PCFG1 ADCS1 RA1 RF1 LATF1 RH1 LATH1 ADON PCFG0 ADCS0 RA0 RF0 LATF0 RH0 LATH0 0000 00-0 ---- -000 0--- -000 --0x 0000 --11 1111 x000 0000 xxxx xxxx 1111 1111 0000 xxxx xxxx xxxx 1111 1111 Value on all other RESETS 0000 000u 0000 0000 0000 0000 0000 0000 -0-- 0000 -0-- 0000 -0-- 0000 uuuu uuuu uuuu uuuu 0000 00-0 ---- -000 0--- -000 --0u 0000 --11 1111 u000 0000 uuuu uuuu 1111 1111 0000 xxxx uuuu uuuu 1111 1111 Bit 7 GIE/ GIEH PSPIF PSPIE PSPIP -- -- -- A/D Result Register A/D Result Register -- -- ADFM -- -- RF7 LATF7 RH7 LATH7 -- -- -- RA6 RF6 LATF6 RH6 LATH6 PORTA Data Direction Register PORTF Data Direction Control Register TRISH(1) PORTH Data Direction Control Register Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'. Shaded cells are not used for A/D conversion. Note 1: Only available on PIC18C858 devices. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 235 PIC18CXX8 NOTES: DS30475A-page 236 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 19.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with the RF1 through RF6 pins. The on-chip Voltage Reference (Section 20.0) can also be an input to the comparators. The CMCON register, shown as Register 19-1, controls the comparator input and output multiplexers. A block diagram of the comparator is shown in Figure 19-1. REGISTER 19-1: CMCON REGISTER R-0 C2OUT bit 7 bit 7 R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 CIS R/W-0 CM2 R/W-0 CM1 R/W-0 CM0 bit 0 C2OUT: Comparator 2 Output When C2INV = 0: 1 = C2 VIN+ > C2 VIN- 0 = C2 VIN+ < C2 VIN- When C2INV = 1: 1 = C2 VIN+ < C2 VIN- 0 = C2 VIN+ > C2 VIN- bit 6 C1OUT: Comparator 1 Output When C1INV = 0: 1 = C1 VIN+ > C1 VIN- 0 = C1 VIN+ < C1 VIN- When C1INV = 1: 1 = C1 VIN+ < C1 VIN- 0 = C1 VIN+ > C1 VIN- bit 5 C2INV: Comparator 2 Output Inversion 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion 1 = C1 Output inverted 0 = C1 Output not inverted CIS: Comparator Input Switch When CM2:CM0 = 110: 1 = C1 VIN- connects to RF5/AN10 C2 VIN- connects to RF3/AN8 0 = C1 VIN- connects to RF6/AN11 C2 VIN- connects to RF4/AN9 CM2:CM0: Comparator Mode Figure 19-1 shows the Comparator modes and CM2:CM0 bit settings Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 4 bit 3 bit 2-0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 237 PIC18CXX8 19.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 19-1 shows the eight possible modes. The TRISF register controls the data direction of the comparator pins for each mode. If the Comparator mode is changed, the comparator output level may not be valid for the specified mode change delay shown in Electrical Specifications (Section 25.0). Note: Comparator interrupts should be disabled during a Comparator mode change. Otherwise, a false interrupt may occur. FIGURE 19-1: COMPARATOR I/O OPERATING MODES Comparators Reset (POR Default Value) CM2:CM0 = 000 RF6/AN11 A VINVIN+ Comparators Off CM2:CM0 = 111 RF6/AN11 D VINVIN+ RF5/AN10 A C1 Off (Read as '0') RF5/AN10 D C1 Off (Read as '0') RF4/AN9 RF3/AN8 A A VINVIN+ RF4/AN9 C2 Off (Read as '0') RF3/AN8 D D VINVIN+ C2 Off (Read as '0') Two Independent Comparators CM2:CM0 = 010 RF6/AN11 A VINVIN+ Two Independent Comparators with Outputs CM2:CM0 = 011 RF6/AN11 A VINVIN+ RF5/AN10 A C1 C1OUT RF5/AN10 A RF2/AN7/C1OUT C1 C1OUT RF4/AN9 RF3/AN8 A A VINVIN+ C2 C2OUT RF4/AN9 RF3/AN8 A A VINVIN+ C2 C2OUT RF1/AN6/C2OUT Two Common Reference Comparators CM2:CM0 = 100 RF6/AN11 A VINVIN+ Two Common Reference Comparators with Outputs CM2:CM0 = 101 RF6/AN11 A VINVIN+ RF5/AN10 A C1 C1OUT RF5/AN10 A RF2/AN7/C1OUT C1 C1OUT RF4/AN9 RF3/AN8 A D VINVIN+ C2 C2OUT RF4/AN9 RF3/AN8 A D VINVIN+ C2 C2OUT RF1/AN6/C2OUT One Independent Comparator with Output CM2:CM0 = 001 RF6/AN11 RF5/AN10 A A VINVIN+ Four Inputs Multiplexed to Two Comparators CM2:CM0 = 110 RF6/AN11 A CIS = 0 CIS = 1 VINVIN+ C1 C1OUT RF5/AN10 A RF4/AN9 A A C1 C1OUT RF2/AN7/C1OUT D D VINVIN+ RF3/AN8 C2 Off (Read as '0') CIS = 0 CIS = 1 VINVIN+ RF4/AN9 RF3/AN8 C2 C2OUT CVREF From VREF Module A = Analog Input, port reads zeros always. D = Digital Input. CIS (CMCON<3>) is the Comparator Input Switch. DS30475A-page 238 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 19.2 Comparator Operation 19.4 Comparator Response Time A single comparator is shown in Figure 19-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level. The shaded areas of the output of the comparator in Figure 19-2 represent the uncertainty due to input offsets and response time. Response time is the minimum time, after selecting a new reference voltage or input source, before the comparator output has a valid level. If the internal reference is changed, the maximum delay of the internal voltage reference must be considered when using the comparator outputs. Otherwise the maximum delay of the comparators should be used (Section 25.0). 19.5 Comparator Outputs 19.3 Comparator Reference An external or internal reference signal may be used depending on the comparator operating mode. The analog signal present at VIN- is compared to the signal at VIN+, and the digital output of the comparator is adjusted accordingly (Figure 19-2). FIGURE 19-2: SINGLE COMPARATOR The comparator outputs are read through the CMCON Register. These bits are read-only. The comparator outputs may also be directly output to the RF1 and RF2 I/O pins. When enabled, multiplexors in the output path of the RF1 and RF2 pins will switch and the output of each pin will be the unsynchronized output of the comparator. The uncertainty of each of the comparators is related to the input offset voltage and the response time given in the specifications. Figure 19-3 shows the comparator output block diagram. The TRISA bits will still function as an output enable/disable for the RF1 and RF2 pins while in this mode. VIN+ VIN- + - Output The polarity of the comparator outputs can be changed using the C2INV and C1INV bits (CMCON<4:5>). Note 1: When reading the PORT register, all pins configured as analog inputs will read as a `0'. Pins configured as digital inputs will convert an analog input, according to the Schmitt Trigger input specification. 2: Analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. VIN- VIN- VIN+ VIN+ Output utput 19.3.1 EXTERNAL REFERENCE SIGNAL When external voltage references are used, the comparator module can be configured to have the comparators operate from the same, or different reference sources. However, threshold detector applications may require the same reference. The reference signal must be between VSS and VDD, and can be applied to either pin of the comparator(s). 19.3.2 INTERNAL REFERENCE SIGNAL The comparator module also allows the selection of an internally generated voltage reference for the comparators. Section 20.0 contains a detailed description of the Comparator Voltage Reference Module that provides this signal. The internal reference signal is used when comparators are in mode CM<2:0> = 110 (Figure 19-1). In this mode, the internal voltage reference is applied to the VIN+ pin of both comparators. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 239 PIC18CXX8 FIGURE 19-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RF1 or RF2 Pin Bus Data Read CMCON Q EN D Set CMIF bit Q From Other Comparator D EN CL Read CMCON RESET DS30475A-page 240 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 19.6 Comparator Interrupts 19.7 Comparator Operation During SLEEP The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred. The CMIF bit (PIR registers) is the comparator interrupt flag. The CMIF bit must be RESET by clearing `0'. Since it is also possible to write a '1' to this register, a simulated interrupt may be initiated. The CMIE bit (PIE registers) and the PEIE bit (INTCON register) must be set to enable the interrupt. In addition, the GIE bit must also be set. If any of these bits are clear, the interrupt is not enabled, though the CMIF bit will still be set if an interrupt condition occurs. . Note: If a change in the CMCON register (C1OUT or C2OUT) should occur when a read operation is being executed (start of the Q2 cycle), then the CMIF (PIR registers) interrupt flag may not get set. A device RESET forces the CMCON register to its RESET state, causing the comparator module to be in the comparator RESET mode, CM<2:0> = 000. This ensures that all potential inputs are analog inputs. Device current is minimized when analog inputs are present at RESET time. The comparators will be powered down during the RESET interval. When a comparator is active and the device is placed in SLEEP mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from SLEEP mode, when enabled. While the comparator is powered up, higher SLEEP currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current, as shown in the comparator specifications. To minimize power consumption while in SLEEP mode, turn off the comparators, CM<2:0> = 111, before entering SLEEP. If the device wakes up from SLEEP, the contents of the CMCON register are not affected. 19.8 Effects of a RESET The user, in the interrupt service routine, can clear the interrupt in the following manner: a) b) Any read or write of CMCON will end the mismatch condition. Clear flag bit CMIF. A mismatch condition will continue to set flag bit CMIF. Reading CMCON will end the mismatch condition, and allow flag bit CMIF to be cleared. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 241 PIC18CXX8 19.9 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 19-4. Since the analog pins are connected to a digital output, they have reverse biased diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6 V in either direction, one of the diodes is forward biased and a latch-up condition may occur. A maximum source impedance of 10 k is recommended for the analog sources. Any external component connected to an analog input pin, such as a capacitor or a Zener diode, should have very little leakage current. FIGURE 19-4: ANALOG INPUT MODEL VDD RS < 10k AIN VA CPIN 5 pF VT = 0.6 V ILEAKAGE 500 nA VT = 0.6 V RIC VSS Legend: CPIN VT ILEAKAGE RIC RS VA = = = = = = Input Capacitance Threshold Voltage Leakage Current at the pin due to various junctions Interconnect Resistance Source Impedance Analog Voltage TABLE 19-1: Name CMCON VRCON INTCON PIR2 PIE2 IPR2 PORTF LATF TRISF REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 6 C1OUT VROE PEIE/ GIEL CMIF CMIE CMIP RF6 LATF6 Bit 5 C2INV VRR TMR0IE -- -- -- RF5 LATF5 Bit 4 C1INV VRSS INTIE -- -- -- RF4 LATF4 Bit 3 CIS VR3 RBIE BCLIF BCLIE BCLIP RF3 LATF3 Bit 2 CM2 VR2 TMR0IF LVDIF LVDIE LVDIP RF2 LATF2 Bit 1 CM1 VR1 INTIF Bit 0 CM0 VR0 RBIF Value on POR Value on All Other RESETS Bit 7 C2OUT VREN GIE/ GIEH -- -- -- RF7 LATF7 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000u TMR3IF CCP2IF -0-- 0000 -0-- 0000 TMR3IE CCP2IE -0-- 0000 -0-- 0000 TMR3IP CCP2IP -1-- 1111 -1-- 1111 RF1 LATF1 RF0 LATF0 x000 0000 u000 0000 xxxx xxxx uuuu uuuu 1111 1111 1111 1111 PORTF Data Direction Register Legend: x = unknown, u = unchanged, - = unimplemented, read as "0" DS30475A-page 242 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 20.0 COMPARATOR VOLTAGE REFERENCE MODULE 20.1 Configuring the Comparator Voltage Reference The Comparator Voltage Reference is a 16-tap resistor ladder network that provides a selectable voltage reference. The resistor ladder is segmented to provide two ranges of CVREF values and has a power-down function to conserve power when the reference is not being used. The CVRCON register controls the operation of the reference as shown in Register 20-1. The block diagram is given in Figure 20-1. The comparator reference supply voltage can come from either VDD or VSS, or the external VREF+ and VREF- that are multiplexed with RA3 and RA2. The comparator reference supply voltage is controlled by the CVRSS bit. The Comparator Voltage Reference can output 16 distinct voltage levels for each range. The equations used to calculate the output of the Comparator Voltage Reference are as follows: If CVRR = 1: CVREF= (CVR<3:0>/24) x CVRSRC If CVRR = 0: CVREF = (CVDD x 1/4) + (CVR<3:0>/32) x CVRSRC The settling time of the Comparator Voltage Reference must be considered when changing the CVREF output (Section 25.0). REGISTER 20-1: VRCON REGISTER R/W-0 VREN bit 7 bit 7 R/W-0 VROE R/W-0 VRR R/W-0 VRSS R/W-0 VR3 R/W-0 VR2 R/W-0 VR1 R/W-0 VR0 bit 0 VREN: Comparator Voltage Reference Enable 1 = CVREF circuit powered on 0 = CVREF circuit powered down VROE: Comparator VREF Output Enable 1 = CVREF voltage level is also output on the RF5/AN10/CVREF pin 0 = CVREF voltage is disconnected from the RF5/AN10/CVREF pin VRR: Comparator VREF Range Selection 1 = 0.00 CVRSRC to 0.75 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size VRSS: Comparator VREF Source Selection 1 = Comparator reference source CVRSRC = VREF+-VREF0 = Comparator reference source CVRSRC = VDD-VSS VR3:VR0: Comparator VREF Value Selection 0 VR3:VR0 15 When VRR = 1: CVREF = (VR<3:0>/ 24) * (CVRSRC) When VRR = 0: CVREF = 1/4 * (CVRSRC) + (VR3:VR0/ 32) * (CVRSRC) Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown bit 6 bit 5 bit 4 bit 3-0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 243 PIC18CXX8 FIGURE 20-1: VOLTAGE REFERENCE BLOCK DIAGRAM VDD VREF+ 16 Stages R R R R CVRR 8R VRSS=0 VRSS=1 VREFCVR3 (From VRCON<3:0>) CVR0 CVRSS=0 CVREN CVRSS=1 8R CVREF 16-1 Analog Mux Note: R is defined in Section 25.0. DS30475A-page 244 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 20.2 Voltage Reference Accuracy/Error 20.5 Connection Considerations The full range of voltage reference cannot be realized due to the construction of the module. The transistors on the top and bottom of the resistor ladder network (Figure 20-1) keep VREF from approaching the reference source rails. The voltage reference is derived from the reference source; therefore, the VREF output changes with fluctuations in that source. The tested absolute accuracy of the voltage reference can be found in Section 25.0. The voltage reference module operates independently of the comparator module. The output of the reference generator may be connected to the RF5 pin if the TRISF<5> bit is set and the VROE bit (VRCON register) is set. Enabling the voltage reference output onto the RF5 pin, with an input signal present, will increase current consumption. Connecting RF5 as a digital output with VRSS enabled will also increase current consumption. The RF5 pin can be used as a simple D/A output with limited drive capability. Due to the limited current drive capability, a buffer must be used on the voltage reference output for external connections to VREF. Figure 20-2 shows an example buffering technique. 20.3 Operation During SLEEP When the device wakes up from SLEEP through an interrupt or a Watchdog Timer time-out, the contents of the VRCON register are not affected. To minimize current consumption in SLEEP mode, the voltage reference should be disabled. 20.4 Effects of a RESET A device RESET disables the voltage reference by clearing bit VREN (VRCON register). This RESET also disconnects the reference from the RA2 pin by clearing bit VROE (VRCON register) and selects the high voltage range by clearing bit CVRR (VRCON register). The VRSS value select bits, CVRCON<3:0>, are also cleared. FIGURE 20-2: VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE CVREF Module R(1) RF5 * Voltage Reference Output Impedance + - * CVREF Output Note 1: R is dependent upon the Voltage Reference Configuration VRCON<3:0> and VRCON<5>. TABLE 20-1: Name VRCON CMCON TRISF REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Bit 6 VROE C1OUT Bit 5 VRR C2INV Bit 4 VRSS C1INV Bit 3 VR3 CIS Bit 2 VR2 CM2 TRISF2 Bit 1 VR1 CM1 TRISF1 Bit 0 VR0 CM0 Value On POR Value On All Other RESETS Bit 7 VREN C2OUT TRISF7 0000 0000 0000 0000 0000 0000 0000 0000 TRISF6 TRISF5 TRISF4 TRISF3 TRISF0 1111 1111 1111 1111 2000 Microchip Technology Inc. Advanced Information DS30475A-page 245 PIC18CXX8 NOTES: DS30475A-page 246 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 21.0 LOW VOLTAGE DETECT In many applications, the ability to determine if the device voltage (VDD) is below a specified voltage level is a desirable feature. A window of operation for the application can be created, where the application software can do "housekeeping tasks" before the device voltage exits the valid operating range. This can be done using the Low Voltage Detect module. This module is software programmable circuitry, where a device voltage trip point can be specified (internal reference voltage or external voltage input). When the voltage of the device becomes lower than the specified point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to that interrupt source. The Low Voltage Detect circuitry is completely under software control. This allows the circuitry to be "turned off" by the software, which minimizes the current consumption for the device. Figure 21-1 shows a possible application voltage curve (typically for batteries). Over time, the device voltage decreases. When the device voltage equals voltage VA, the LVD logic generates an interrupt. This occurs at time TA. The application software then has the time, until the device voltage is no longer in valid operating range, to shut down the system. Voltage point VB is the minimum valid operating voltage specification. This occurs at time TB. TB - TA is the total time for shutdown. Figure 21-2 shows the block diagram for the LVD module. A comparator uses an internally generated reference voltage as the set point. When the selected tap output of the device voltage crosses the set point (is lower than), the LVDIF bit (PIR registers) is set. Each node in the resister divider represents a "trip point" voltage. The "trip point" voltage is the minimum supply voltage level at which the device can operate before the LVD module asserts an interrupt. When the supply voltage is equal to the trip point, the voltage tapped off of the resistor array (or external LVDIN input pin) is equal to the voltage generated by the internal voltage reference module. The comparator then generates an interrupt signal setting the LVDIF bit. This voltage is software programmable to any one of 16 values (See Figure 21-2). The trip point is selected by programming the LVDL3:LVDL0 bits (LVDCON<3:0>). FIGURE 21-2: LOW VOLTAGE DETECT (LVD) BLOCK DIAGRAM VDD LVDIN LVD Control Register FIGURE 21-1: TYPICAL LOW VOLTAGE DETECT APPLICATION 16 to 1 MUX LVDIF Voltage VA VB LVDEN Internally Generated Reference Voltage Time TA TB Legend: VA = LVD trip point VB = Minimum valid device operating range 2000 Microchip Technology Inc. Advanced Information DS30475A-page 247 PIC18CXX8 21.1 Control Register The Low Voltage Detect Control register (Register 21-1) controls the operation of the Low Voltage Detect circuitry. REGISTER 21-1: LVDCON REGISTER U-0 -- bit 7 U-0 -- R-0 IRVST R/W-0 LVDEN R/W-0 LVDL3 R/W-1 LVDL2 R/W-0 LVDL1 R/W-1 LVDL0 bit 0 bit 7-6 bit 5 Unimplemented: Read as '0' IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled LVDEN: Low Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit LVDL3:LVDL0: Low Voltage Detection Limit bits 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = 4.5V min - 4.77V max. 1101 = 4.2V min - 4.45V max. 1100 = 4.0V min - 4.24V max.; Reserved on PIC18CXX8 1011 = 3.8V min - 4.03V max.; Reserved on PIC18CXX8 1010 = 3.6V min - 3.82V max.; Reserved on PIC18CXX8 1001 = 3.5V min - 3.71V max.; Reserved on PIC18CXX8 1000 = 3.3V min - 3.50V max.; Reserved on PIC18CXX8 0111 = 3.0V min - 3.18V max.; Reserved on PIC18CXX8 0110 = 2.8V min - 2.97V max.; Reserved on PIC18CXX8 0101 = 2.7V min - 2.86V max.; Reserved on PIC18CXX8 0100 = 2.5V min - 2.65V max.; Reserved on PIC18CXX8 0011 = Reserved on PIC18CXX8 and PIC18LCXX8 0010 = Reserved on PIC18CXX8 and PIC18LCXX8 0001 = Reserved on PIC18CXX8 and PIC18LCXX8 0000 = Reserved on PIC18CXX8 and PIC18LCXX8 Note: LVDL3:LVDL0 modes which result in a trip point below the valid operating voltage of the device are not tested. bit 4 bit 3-0 Legend: R = Readable bit - n = Value at POR W = Writable bit '1' = Bit is set U = Unimplemented bit, read as `0' '0' = Bit is cleared x = Bit is unknown DS30475A-page 248 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 21.2 Operation The following steps are needed to setup the LVD module: 1. Write the value to the LVDL3:LVDL0 bits (LVDCON register), which selects the desired LVD Trip Point. Ensure that LVD interrupts are disabled (the LVDIE bit is cleared or the GIE bit is cleared). Enable the LVD module (set the LVDEN bit in the LVDCON register). Wait for the LVD module to stabilize (the IRVST bit to become set). Clear the LVD interrupt flag, which may have falsely become set, until the LVD module has stabilized (clear the LVDIF bit). Enable the LVD interrupt (set the LVDIE and the GIE bits). Depending on the power source for the device voltage, the voltage normally decreases relatively slowly. This means that the LVD module does not need to be constantly operating. To decrease current consumption, the LVD circuitry only needs to be enabled for short periods, where the voltage is checked. After doing the check, the LVD module may be disabled. Each time that the LVD module is enabled, the circuitry requires some time to stabilize. After the circuitry has stabilized, all status flags may be cleared. The module will then indicate the proper state of the system. 2. 3. 4. 5. 6. Figure 21-3 shows typical waveforms that the LVD module may be used to detect. FIGURE 21-3: LOW VOLTAGE DETECT WAVEFORMS CASE 1: LVDIF may not be set VDD . VLVD LVDIF Enable LVD Internally Generated Reference Stable 50 ms LVDIF cleared in software CASE 2: VDD VLVD LVDIF Enable LVD Internally Generated Reference Stable 50 ms LVDIF cleared in software LVDIF cleared in software, LVDIF remains set since LVD condition still exists 2000 Microchip Technology Inc. Advanced Information DS30475A-page 249 PIC18CXX8 21.2.1 REFERENCE VOLTAGE SET POINT 21.4 Operation During SLEEP The Internal Reference Voltage of the LVD module may be used by other internal circuitry (the programmable Brown-out Reset). If these circuits are disabled (lower current consumption), the reference voltage circuit requires time to become stable before a low voltage condition can be reliably detected. This time is invariant of system clock speed. This start-up time is specified in electrical specification parameter #36. The low voltage interrupt flag will not be enabled until a stable reference voltage is reached. Refer to the waveform in Figure 21-3. 21.2.2 CURRENT CONSUMPTION When enabled, the LVD circuitry continues to operate during SLEEP. If the device voltage crosses the trip point, the LVDIF bit will be set and the device will wakeup from SLEEP. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. 21.5 Effects of a RESET A device RESET forces all registers to their RESET state. This forces the LVD module to be turned off. When the module is enabled, the LVD comparator and voltage divider are enabled and will consume static current. The voltage divider can be tapped from multiple places in the resistor array. Total current consumption, when enabled, is specified in electrical specification parameter #D022B. 21.3 External Analog Voltage Input The LVD module has an additional feature that allows the user to supply the trip point voltage to the module from an external source (the LVDIN pin). The LVDIN pin is used as the trip point when the LVDL3:LVDL0 bits = '1111'. This state connects the LVDIN pin voltage to the comparator. The other comparator input is connected to an internal reference voltage source. DS30475A-page 250 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 22.0 SPECIAL FEATURES OF THE CPU SLEEP mode is designed to offer a very low current Power-down mode. The user can wake-up from SLEEP through external RESET, Watchdog Timer Wake-up or through an interrupt. Several oscillator options are also made available to allow the part to fit the application. The RC oscillator option saves system cost, while the LP crystal option saves power. A set of configuration bits are used to select various options. There are several features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection: * OSC Selection * RESET - Power-on Reset (POR) - Power-up Timer (PWRT) - Oscillator Start-up Timer (OST) - Programmable Brown-out Reset (BOR) * Interrupts * Watchdog Timer (WDT) * SLEEP * Code Protection * ID Locations * In-circuit Serial Programming PIC18CXX8 devices have a Watchdog Timer, which is permanently enabled via the configuration bits or it can be software-controlled. It runs off its own RC oscillator for added reliability. There are two timers that offer necessary delays on power-up. One is the Oscillator Start-up Timer (OST), intended to keep the chip in RESET until the crystal oscillator is stable. The other is the Power-up Timer (PWRT), which provides a fixed delay on power-up only, designed to keep the part in RESET while the power supply stabilizes. With these two timers on-chip, most applications need no external RESET circuitry. 22.1 Configuration Bits The configuration bits can be programmed (read as '0'), or left unprogrammed (read as '1'), to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h - 3FFFFFh), which can only be accessed using table reads and table writes. TABLE 22-1: Filename 300000h 300001h 300002h 300003h 300006h CONFIGURATION BITS AND DEVICE ID'S Bit 7 CP r -- -- -- DEV2 DEV10 Bit 6 CP r -- -- -- DEV1 DEV9 Bit 5 CP OSCSEN -- -- -- DEV0 DEV8 Bit 4 CP -- -- -- -- REV4 DEV7 Bit 3 CP -- BORV1 WDTPS2 -- REV3 DEV6 Bit 2 CP FOSC2 BORV0 WDTPS1 -- REV2 DEV5 Bit 1 CP FOSC1 BODEN WDTPS0 r REV1 DEV4 Bit 0 CP FOSC0 PWRTEN WDTEN STVREN REV0 DEV3 Default/ Unprogrammed Value 1111 1111 111- -111 ---- 1111 ---- 1111 ---- --11 1111 1111 1111 1111 CONFIG1L CONFIG1H CONFIG2L CONFIG2H CONFIG4L 3FFFFEh DEVID1 3FFFFFh DEVID2 Legend: x = unknown, u = unchanged, - = unimplemented, q = value depends on condition, r = reserved. Grayed cells are unimplemented, read as '0'. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 251 PIC18CXX8 REGISTER 22-1: CONFIGURATION REGISTER 1 LOW (CONFIG1L: BYTE ADDRESS 0x300000) R/P-1 CP bit 7 bit 7-0 CP: Code Protection bits (apply when in Code Protected Microcontroller mode) 1 = Program memory code protection off 0 = All of program memory code protected Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed R/P-1 CP R/P-1 CP R/P-1 CP R/P-1 CP R/P-1 CP R/P-1 CP R/P-1 CP bit 0 REGISTER 22-2: CONFIGURATION REGISTER 1 HIGH (CONFIG1H: BYTE ADDRESS 0x300001) R/P-1 Reserved bit 7 R/P-1 Reserved R/P-1 OSCSEN U-0 -- U-0 -- R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0 bit 7-6 bit 5 Reserved: Maintain this bit set OSCSEN: Oscillator System Clock Switch Enable bit 1 = Oscillator system clock switch option is disabled (Main oscillator is source) 0 = Oscillator system clock switch option is enabled (Oscillator switching is enabled) Unimplemented: Read as '0' FOSC2:FOSC0: Oscillator Selection bits 111 = RC oscillator w/ OSC2 configured as RA6 110 = HS4 oscillator with PLL enabled/Clock frequency = (4 x Fosc) 101 = EC oscillator w/ OSC2 configured as RA6 100 = EC oscillator w/ OSC2 configured as divide by 4 clock output 011 = RC oscillator 010 = HS oscillator 001 = XT oscillator 000 = LP oscillator Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed bit 4-3 bit 2-0 DS30475A-page 252 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 REGISTER 22-3: CONFIGURATION REGISTER 2 LOW (CONFIG2L: BYTE ADDRESS 0x300002) U-0 -- bit 7 bit 7-4 bit 3-2 Unimplemented: Read as '0' BORV1:BORV0: Brown-out Reset Voltage bits 11 =VBOR set to 2.5V 10 =VBOR set to 2.7V 01 =VBOR set to 4.2V 00 =VBOR set to 4.5V BOREN: Brown-out Reset Enable bit(1) 1 = Brown-out Reset enabled 0 = Brown-out Reset disabled PWRTEN: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled Note 1: Enabling Brown-out Reset automatically enables the Power-up Timer (PWRT), regardless of the value of bit PWRTEN. Ensure the Power-up Timer is enabled any time Brown-out Reset is enabled. Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- R/P-1 BORV1 R/P-1 BORV0 R/P-1 BOREN R/P-1 PWRTEN bit 0 bit 1 bit 0 REGISTER 22-4: CONFIGURATION REGISTER 2 HIGH (CONFIG2H: BYTE ADDRESS 0x300003) U-0 -- bit 7 U-0 -- U-0 -- U-0 -- R/P-1 WDTPS2 R/P-1 R/P-1 R/P-1 WDTEN bit 0 WDTPS1 WDTPS0 bit 7-4 bit 3-1 Unimplemented: Read as '0' WDTPS2:WDTPS0: Watchdog Timer Postscale Select bits 000 = 1:128 001 = 1:64 010 = 1:32 011 = 1:16 100 = 1:8 101 = 1:4 110 = 1:2 111 = 1:1 WDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed bit 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 253 PIC18CXX8 REGISTER 22-5: CONFIGURATION REGISTER 4 LOW (CONFIG4L: BYTE ADDRESS 0x300006) U-0 -- bit 7 bit 7-2 bit 1 bit 0 Unimplemented: Read as '0' Reserved: Maintain this bit set STVREN: Stack Full/Underflow RESET Enable bit 1 = Stack Full/Underflow will cause RESET 0 = Stack Full/Underflow will not cause RESET Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as `0' u = Unchanged from programmed state - n = Value when device is unprogrammed U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/P-1 Reserved R/P-1 STVREN bit 0 DS30475A-page 254 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 22.2 Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscillator, which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin. That means that the WDT will run, even if the clock on the OSC1/CLKI and OSC2/CLKO/RA6 pins of the device has been stopped; for example, by execution of a SLEEP instruction. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is in SLEEP mode, a WDT time-out causes the device to wake-up and continue with normal operation (Watchdog Timer Wake-up). The TO bit in the RCON register will be cleared upon a WDT time-out. The Watchdog Timer is enabled/disabled by a device configuration bit. If the WDT is enabled, software execution may not disable this function. When the WDTEN configuration bit is cleared, the SWDTEN bit enables/disables the operation of the WDT. The WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT postscaler may be assigned using the configuration bits. Note: The CLRWDT and SLEEP instructions clear the WDT and the postscaler if assigned to the WDT, and prevent it from timing out and generating a device RESET condition. Note: When a CLRWDT instruction is executed and the prescaler is assigned to the WDT, the prescaler count will be cleared, but the prescaler assignment is not changed. CONTROL REGISTER 22.2.1 Register 22-6 shows the WDTCON register. This is a readable and writable register, which contains a control bit that allows software to override the WDT enable configuration bit, only when the configuration bit has disabled the WDT. REGISTER 22-6: WDTCON REGISTER U-0 -- bit 7 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 SWDTEN bit 0 bit 7-1 bit 0 Unimplemented: Read as '0' SWDTEN: Software Controlled Watchdog Timer Enable bit 1 = Watchdog Timer is on 0 = Watchdog Timer is turned off if the WDTEN configuration bit in the configuration register = '0' Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' - n = Value at POR 2000 Microchip Technology Inc. Advanced Information DS30475A-page 255 PIC18CXX8 22.2.2 WDT POSTSCALER The WDT has a postscaler that can extend the WDT Reset period. The postscaler is selected at the time of the device programming, by the value written to the CONFIG2H configuration register. FIGURE 22-1: WATCHDOG TIMER BLOCK DIAGRAM WDT Timer Postscaler 8 8 - to - 1 MUX WDTPS2:WDTPS0 WDTEN Configuration bit SWDTEN bit WDT Time-out Note: WDPS2:WDPS0 are bits in a configuration register. TABLE 22-2: Name CONFIG2H RCON WDTCON SUMMARY OF WATCHDOG TIMER REGISTERS Bit 7 -- IPEN -- Bit 6 -- LWRT -- Bit 5 -- -- -- Bit 4 -- RI -- Bit 3 WDTPS2 TO -- Bit 2 WDTPS2 PD -- Bit 1 WDTPS0 POR -- Bit 0 WDTEN BOR SWDTEN Legend: Shaded cells are not used by the Watchdog Timer. DS30475A-page 256 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 22.3 Power-down Mode (SLEEP) The following peripheral interrupts can wake the device from SLEEP: PSP read or write. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. TMR3 interrupt. Timer3 must be operating as an asynchronous counter. 4. CCP Capture mode interrupt. 5. Special event trigger (Timer1 in Asynchronous mode using an external clock). 6. MSSP (START/STOP) bit detect interrupt. 7. MSSP transmit or receive in Slave mode (SPI/I2C). 8. USART RX or TX (Synchronous Slave mode). 9. A/D conversion (when A/D clock source is RC). 10. Activity on CAN bus receive line. Other peripherals cannot generate interrupts, since during SLEEP, no on-chip clocks are present. External MCLR Reset will cause a device RESET. All other events are considered a continuation of program execution and will cause a "wake-up". The TO and PD bits in the RCON register can be used to determine the cause of the device RESET. The PD bit, which is set on power-up, is cleared when SLEEP is invoked. The TO bit is cleared, if a WDT time-out occurred (and caused wake-up). When the SLEEP instruction is being executed, the next instruction (PC + 2) is pre-fetched. For the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be set (enabled). Wake-up is regardless of the state of the GIE bit. If the GIE bit is clear (disabled), the device continues execution at the instruction after the SLEEP instruction. If the GIE bit is set (enabled), the device executes the instruction after the SLEEP instruction and then branches to the interrupt address. In cases where the execution of the instruction following SLEEP is not desirable, the user should have a NOP after the SLEEP instruction. 1. 2. Power-down mode is entered by executing a SLEEP instruction. Upon entering into Power-down mode, the following actions are performed: 1. 2. 3. 4. 5. Watchdog Timer is cleared and kept running. PD bit in RCON register is cleared. TO bit in RCON register is set. Oscillator driver is turned off. I/O ports maintain the status they had before the SLEEP instruction was executed. To achieve lowest current consumption, follow these steps before switching to Power-down mode: 1. Place all I/O pins at either VDD or VSS and ensure no external circuitry is drawing current from I/O pin. Power-down A/D and external clocks. Pull all hi-impedance inputs to high or low externally. Place T0CKI at VSS or VDD. Current consumption by PORTB on-chip pull-ups should be taken into account and disabled if necessary. 2. 3. 4. 5. The MCLR pin must be at a logic high level (VIHMC). 22.3.1 WAKE-UP FROM SLEEP The device can wake-up from SLEEP through one of the following events: 1. 2. 3. External RESET input on MCLR pin. Watchdog Timer Wake-up (if WDT was enabled). Interrupt from INT pin, RB port change or a Peripheral Interrupt. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 257 PIC18CXX8 22.3.2 WAKE-UP USING INTERRUPTS When global interrupts are disabled (GIE cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: * If an interrupt condition (interrupt flag bit and interrupt enable bits are set) occurs before the execution of a SLEEP instruction, the SLEEP instruction will complete as a NOP. Therefore, the WDT and WDT postscaler will not be cleared, the TO bit will not be set and PD bits will not be cleared. * If the interrupt condition occurs during or after the execution of a SLEEP instruction, the device will immediately wake-up from sleep. The SLEEP instruction will be completely executed before the wake-up. Therefore, the WDT and WDT postscaler will be cleared, the TO bit will be set and the PD bit will be cleared. Even if the flag bits were checked before executing a SLEEP instruction, it may be possible for flag bits to become set before the SLEEP instruction completes. To determine whether a SLEEP instruction executed, test the PD bit. If the PD bit is set, the SLEEP instruction was executed as a NOP. To ensure that the WDT is cleared, a CLRWDT instruction should be executed before a SLEEP instruction. FIGURE 22-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT(1,2) Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) INT pin INTIF bit GIEH bit Processor in SLEEP INSTRUCTION FLOW PC Instruction fetched Instruction executed PC Inst(PC) = SLEEP Inst(PC - 1) PC+2 Inst(PC + 2) SLEEP PC+4 PC+4 Inst(PC + 4) Inst(PC + 2) Dummy cycle PC + 4 0008h Inst(0008h) Dummy cycle 000Ah Inst(000Ah) Inst(0008h) Interrupt Latency(3) TOST(2) Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Note 1: 2: 3: 4: XT, HS or LP oscillator mode assumed. GIE set is assumed. In this case, after wake- up, the processor jumps to the interrupt routine. If GIE is cleared, execution will continue in-line. TOST = 1024TOSC (drawing not to scale). This delay will not occur for RC and EC osc modes. CLKOUT is not available in these oscillator modes, but shown here for timing reference. DS30475A-page 258 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 22.4 Program Verification/Code Protection 22.6 In-Circuit Serial Programming If the code protection bit(s) have not been programmed, the on-chip program memory can be read out for verification purposes. Note: Microchip Technology does not recommend code protecting windowed devices. PIC18CXX8 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 22.5 ID Locations Five memory locations (200000h - 200004h) are designated as ID locations, where the user can store checksum or other code identification numbers. These locations are accessible during normal execution through the TBLRD instruction, or during program/verify. The ID locations can be read when the device is code protected. 22.7 Device ID Bits Device ID bits are located in program memory at 3FFFFEh and 3FFFFFh. The Device ID bits are used by programmers to retrieve part number and revision information about a device. These registers may also be accessed using a TBLRD instruction (Register 22-8 and Register 22-7). REGISTER 22-7: DEVID1 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFE) R/P-1 DEV2 bit 7 R/P-1 DEV1 R/P-1 DEV0 R/P-1 REV4 R/P-1 REV3 R/P-1 REV2 R/P-1 REV1 R/P-1 REV0 bit 0 bit 7-5 DEV2:DEV0: Device ID bits These bits are used with the DEV10:DEV3 bits in the Device ID register 2 to identify the part number REV4:REV0: Revision ID bits These bits are used to indicate the revision of the device Legend: R = Readable bit U = Unimplemented bit, read as `0' P = Programmable bit - n = Unprogrammed Value (x = unknown) bit 4-0 REGISTER 22-8: DEVID2 ID REGISTER FOR THE PIC18CXX8 DEVICE (0x3FFFFF) R/P-1 DEV10 bit 7 R/P-1 DEV9 R/P-1 DEV8 R/P-1 DEV7 R/P-1 DEV6 R/P-1 DEV5 R/P-1 DEV4 R/P-1 DEV3 bit 0 bit 7-0 DEV10:DEV3: Device ID bits These bits are used with the DEV2:DEV0 bits in the Device ID register 1 to identify the part number Legend: R = Readable bit U = Unimplemented bit, read as `0' P = Programmable bit - n = Unprogrammed Value (x = unknown) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 259 PIC18CXX8 NOTES: DS30475A-page 260 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 23.0 INSTRUCTION SET SUMMARY The PIC18CXX8 instruction set adds many enhancements to the previous PICmicro(R) instruction sets, while maintaining an easy migration from these PICmicro instruction sets. Most instructions are a single program memory word (16-bits), but there are three instructions that require two program memory locations. Each single word instruction is a 16-bit word divided into an OPCODE, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Byte-oriented operations Bit-oriented operations Literal operations Control operations The control instructions may use some of the following operands: * A program memory address (specified by the value of 'n') * The mode of the Call or Return instructions (specified by the value of 's') * The mode of the Table Read and Table Write instructions (specified by the value of 'm') * No operand required (specified by the value of '--') All instructions are a single word, except for four double word instructions. These three instructions were made double word instructions so that all the required information is available in these 32-bits. In the second word, the 4-MSb's are 1's. If this second word is executed as an instruction (by itself), it will execute as a NOP. All single word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. The double word instructions execute in two instruction cycles. One instruction cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 s. If a conditional test is true or the program counter is changed as a result of an instruction, the instruction execution time is 2 s. Two word branch instructions (if true) would take 3 s. Figure 23-1 shows the general formats that the instructions can have. All examples use the following format to represent a hexadecimal number: 0xhh where h signifies a hexadecimal digit. The Instruction Set Summary, shown in Table 23-2, lists the instructions recognized by the Microchip assembler (MPASMTM). Section 23.1 provides a description of each instruction. The PIC18CXX8 instruction set summary in Table 23-2 lists byte-oriented, bit-oriented, literal and control operations. Table 23-1 shows the opcode field descriptions. Most byte-oriented instructions have three operands: 1. 2. 3. The file register (specified by the value of 'f') The destination of the result (specified by the value of 'd') The accessed memory (specified by the value of 'a') 'f' represents a file register designator and 'd' represents a destination designator. The file register designator specifies which file register is to be used by the instruction. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is placed in the WREG register. If 'd' is one, the result is placed in the file register specified in the instruction. All bit-oriented instructions have three operands: 1. 2. 3. The file register (specified by the value of 'f') The bit in the file register (specified by the value of 'b') The accessed memory (specified by the value of 'a') 'b' represents a bit field designator which selects the number of the bit affected by the operation, while 'f' represents the number of the file in which the bit is located. The literal instructions may use some of the following operands: * A literal value to be loaded into a file register (specified by the value of 'k') * The desired FSR register to load the literal value into (specified by the value of 'f') * No operand required (specified by the value of '--') 2000 Microchip Technology Inc. Advanced Information DS30475A-page 261 PIC18CXX8 TABLE 23-1: Field a OPCODE FIELD DESCRIPTIONS Description RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register ACCESS = 0: RAM access bit symbol BANKED = 1: RAM access bit symbol Bit address within an 8-bit file register (0 to 7) Bank Select Register. Used to select the current RAM bank. Destination select bit; d = 0: store result in WREG, d = 1: store result in file register f. Destination either the WREG register or the specified register file location 8-bit Register file address (0x00 to 0xFF) 12-bit Register file address (0x000 to 0xFFF). This is the source address. 12-bit Register file address (0x000 to 0xFFF). This is the destination address. ACCESS BANKED bbb BSR d dest f fs fd k label mm Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value) Label name The mode of the TBLPTR register for the Table Read and Table Write instructions Only used with Table Read and Table Write instructions: * No Change to register (such as TBLPTR with Table reads and writes) *+ Post-Increment register (such as TBLPTR with Table reads and writes) *Post-Decrement register (such as TBLPTR with Table reads and writes) +* Pre-Increment register (such as TBLPTR with Table reads and writes) n The relative address (2's complement number) for relative branch instructions, or the direct address for Call/Branch and Return instructions PRODH Product of Multiply high byte (Register at address 0xFF4) PRODL Product of Multiply low byte (Register at address 0xFF3) s Fast Call / Return mode select bit. s = 0: do not update into/from shadow registers s = 1: certain registers loaded into/from shadow registers (Fast mode) u Unused or Unchanged (Register at address 0xFE8) W W = 0: Destination select bit symbol WREG Working register (accumulator) (Register at address 0xFE8) x Don't care (0 or 1) The assembler will generate code with x = 0. It is the recommended form of use for compatibility with all Microchip software tools. TBLPTR 21-bit Table Pointer (points to a Program Memory location) (Register at address 0xFF6) TABLAT 8-bit Table Latch (Register at address 0xFF5) TOS Top-of-Stack PC Program Counter PCL Program Counter Low Byte (Register at address 0xFF9) PCH Program Counter High Byte PCLATH Program Counter High Byte Latch (Register at address 0xFFA) PCLATU Program Counter Upper Byte Latch (Register at address 0xFFB) GIE Global Interrupt Enable bit WDT Watchdog Timer TO Time-out bit PD Power-down bit C, DC, Z, OV, N ALU status bits Carry, Digit Carry, Zero, Overflow, Negative [] Optional () Contents Assigned to <> Register bit field In the set of italics User defined term (font is courier) DS30475A-page 262 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 23-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 OPCODE 9 d 87 a 0 f (FILE #) ADDWF MYREG, W, B Example Instruction d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 12 11 1111 0 f (Source FILE #) 0 f (Destination FILE #) MOVFF MYREG1, MYREG2 f = 12-bit file register address Bit-oriented file register operations 15 12 11 9 87 OPCODE b (BIT #) a 0 f (FILE #) BSF MYREG, bit, B b = 3-bit position of bit in file register (f) a = 0 to force Access Bank a = 1 for BSR to select Bank f = 8-bit file register address Literal operations 15 OPCODE k = 8-bit immediate value Control operations CALL, GOTO and Branch operations 15 OPCODE 15 1111 8 7 k (literal) 0 MOVLW 0x7F 87 n<7:0> (literal) 0 GOTO Label 12 11 n<19:8> (literal) 0 n = 20-bit immediate value 15 OPCODE 15 1111 87 S n<7:0> (literal) 0 CALL MYFUNC 12 11 n<19:8> (literal) S = Fast bit 0 15 OPCODE 15 OPCODE 11 10 n<10:0> (literal) 87 n<7:0> (literal) 0 BRA MYFUNC 0 BC MYFUNC 15 OPCODE 15 1111 6 f 11 0000 4 k (literal) 7 k (literal) 0 LFSR FSR0, 0x100 0 2000 Microchip Technology Inc. Advanced Information DS30475A-page 263 PIC18CXX8 TABLE 23-2: Mnemonic, Operands PIC18CXX8 INSTRUCTION SET 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS f [,d] [,a] Add WREG and f 0010 01da ffff ffff C, DC, Z, OV, N 1, 2, 6 ADDWF 1 0010 00da ffff ffff C, DC, Z, OV, N 1, 2, 6 ADDWFC f [,d] [,a] Add WREG and Carry bit to f 1 1,2, 6 f [,d] [,a] AND WREG with f 0001 01da ffff ffff Z, N ANDWF 1 2, 6 f [,a] 0110 101a ffff ffff Z CLRF 1 Clear f 1, 2, 6 f [,d] [,a] Complement f 0001 11da ffff ffff Z, N COMF 1 4, 6 CPFSEQ f [,a] 1 (2 or 3) 0110 001a ffff ffff None Compare f with WREG, skip = 4, 6 CPFSGT f [,a] 1 (2 or 3) 0110 010a ffff ffff None Compare f with WREG, skip > 1, 2, 6 CPFSLT f [,a] 1 (2 or 3) 0110 000a ffff ffff None Compare f with WREG, skip < f [,d] [,a] Decrement f 0000 01da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6 DECF 1 1, 2, 3, 4, 6 DECFSZ f [,d] [,a] Decrement f, Skip if 0 1 (2 or 3) 0010 11da ffff ffff None 1, 2, 6 DCFSNZ f [,d] [,a] Decrement f, Skip if Not 0 1 (2 or 3) 0100 11da ffff ffff None f [,d] [,a] Increment f 0010 10da ffff ffff C, DC, Z, OV, N 1, 2, 3, 4, 6 INCF 1 4, 6 f [,d] [,a] Increment f, Skip if 0 INCFSZ 1 (2 or 3) 0011 11da ffff ffff None 1, 2, 6 f [,d] [,a] Increment f, Skip if Not 0 INFSNZ 1 (2 or 3) 0100 10da ffff ffff None 1, 2, 6 f [,d] [,a] Inclusive OR WREG with f 0001 00da ffff ffff Z, N IORWF 1 1, 6 f [,d] [,a] Move f 0101 00da ffff ffff Z, N MOVF 1 fs, fd 1100 ffff ffff ffff None MOVFF 2 Move fs (source) to 1st word 1111 ffff ffff ffff fd (destination)2nd word 6 0110 111a ffff ffff None MOVWF f [,a] 1 Move WREG to f 6 0000 001a ffff ffff None MULWF 1 Multiply WREG with f f [,a] 0110 110a ffff ffff C, DC, Z, OV, N 1, 2, 6 NEGF 1 Negate f f [,a] 6 0011 01da ffff ffff C, Z, N RLCF 1 f [,d] [,a] Rotate Left f through Carry 1, 2, 6 0100 01da ffff ffff Z, N RLNCF 1 f [,d] [,a] Rotate Left f (No Carry) 6 0011 00da ffff ffff C, Z, N RRCF 1 f [,d] [,a] Rotate Right f through Carry 6 0100 00da ffff ffff Z, N RRNCF 1 f [,d] [,a] Rotate Right f (No Carry) 6 0110 100a ffff ffff None SETF 1 Set f f [,a] 0101 01da ffff ffff C, DC, Z, OV, N 1, 2, 6 SUBFWB f [,d] [,a] Subtract f from WREG with 1 borrow 0101 11da ffff ffff C, DC, Z, OV, N 6 SUBWF 1 f [,d] [,a] Subtract WREG from f 0101 10da ffff ffff C, DC, Z, OV, N 1, 2, 6 SUBWFB f [,d] [,a] Subtract WREG from f with 1 borrow 4, 6 0011 10da ffff ffff None SWAPF 1 f [,d] [,a] Swap nibbles in f 1, 2, 6 TSTFSZ f [,a] 1 (2 or 3) 0110 011a ffff ffff None Test f, skip if 0 6 0001 10da ffff ffff Z, N XORWF 1 f [,d] [,a] Exclusive OR WREG with f BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b [,a] Bit Clear f 1 1001 bbba ffff ffff None 1, 2, 6 BSF f, b [,a] Bit Set f 1 1000 bbba ffff ffff None 1, 2, 6 BTFSC f, b [,a] Bit Test f, Skip if Clear 1 (2 or 3) 1011 bbba ffff ffff None 3, 4, 6 BTFSS f, b [,a] Bit Test f, Skip if Set 1 (2 or 3) 1010 bbba ffff ffff None 3, 4, 6 BTG f [,d] [,a] Bit Toggle f 1 0111 bbba ffff ffff None 1, 2, 6 Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0' according to address of register being used. DS30475A-page 264 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 23-2: Mnemonic, Operands PIC18CXX8 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 1 (2) 1 (2) 2 1 1 2 1 1 1 1 2 1 2 1110 1110 1110 1110 1110 1110 1110 1101 1110 1110 1111 0000 0000 1110 1111 0000 1111 0000 0000 1101 0000 0000 0010 0110 0011 0111 0101 0001 0100 0nnn 0000 110s kkkk 0000 0000 1111 kkkk 0000 xxxx 0000 0000 1nnn 0000 0000 nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0000 0000 kkkk kkkk 0000 xxxx 0000 0000 nnnn 1111 0001 LSb nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn nnnn kkkk kkkk 0100 0111 kkkk kkkk 0000 xxxx 0110 0101 nnnn 1111 000s Status Affected Notes None None None None None All GIE/GIEH, PEIE/GIEL RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None RETURN s Return from Subroutine 2 0000 0000 0001 001s None SLEEP -- Go into Standby mode 1 0000 0000 0000 0011 TO, PD Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0' according to address of register being used. CONTROL OPERATIONS BC n Branch if Carry BN n Branch if Negative BNC n Branch if Not Carry BNN n Branch if Not Negative BNOV n Branch if Not Overflow BNZ n Branch if Not Zero BOV n Branch if Overflow BRA n Branch Unconditionally BZ n Branch if Zero CALL n, s Call subroutine1st word 2nd word CLRWDT -- Clear Watchdog Timer DAW -- Decimal Adjust WREG GOTO n Go to address1st word 2nd word NOP -- No Operation NOP -- No Operation (Note 4) POP -- Pop top of return stack (TOS) PUSH -- Push top of return stack (TOS) RCALL n Relative Call RESET Software device RESET RETFIE s Return from interrupt enable None None None None None None None None None None TO, PD C None 2000 Microchip Technology Inc. Advanced Information DS30475A-page 265 PIC18CXX8 TABLE 23-2: Mnemonic, Operands PIC18CXX8 INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW k Add literal and WREG 1 0000 1111 kkkk kkkk C, DC, Z, OV, N ANDLW k AND literal with WREG 1 0000 1011 kkkk kkkk Z, N IORLW k Inclusive OR literal with WREG 1 0000 1001 kkkk kkkk Z, N LFSR f, k Load FSR(f) with a 12-bit 2 1110 1110 00ff kkkk None literal (k) 1111 0000 kkkk kkkk MOVLB k Move literal to BSR<3:0> 1 0000 0001 0000 kkkk None MOVLW k Move literal to WREG 1 0000 1110 kkkk kkkk None MULLW k Multiply literal with WREG 1 0000 1101 kkkk kkkk None RETLW k Return with literal in WREG 2 0000 1100 kkkk kkkk None SUBLW k Subtract WREG from literal 1 0000 1000 kkkk kkkk C, DC, Z, OV, N XORLW k Exclusive OR literal with WREG 1 0000 1010 kkkk kkkk Z, N DATA MEMORY PROGRAM MEMORY OPERATIONS TBLRD* Table Read 2 0000 0000 0000 1000 None TBLRD*+ Table Read with post-increment 0000 0000 0000 1001 None TBLRD*Table Read with post-decrement 0000 0000 0000 1010 None TBLRD+* Table Read with pre-increment 0000 0000 0000 1011 None TBLWT* Table Write 2 (5) 0000 0000 0000 1100 None TBLWT*+ Table Write with post-increment 0000 0000 0000 1101 None TBLWT*Table Write with post-decrement 0000 0000 0000 1110 None TBLWT+* Table Write with pre-increment 0000 0000 0000 1111 None Note 1: When a PORT register is modified as a function of itself (e.g., MOVF PORTB, 1, 0), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. 4: Some instructions are 2 word instructions. The second word of these instructions will be executed as a NOP, unless the first word of the instruction retrieves the information embedded in these 16-bits. This ensures that all program memory locations have a valid instruction. 5: If the table write starts the write cycle to internal memory, the write will continue until terminated. 6: Microchip Assembler MASM automatically defaults destination bit 'd' to '1', while access bit 'a' defaults to '1' or '0' according to address of register being used. DS30475A-page 266 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 23.1 ADDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Instruction Set ADD literal to W [ label ] ADDLW 0 k 255 (WREG) + k WREG N,OV, C, DC, Z 0000 1111 kkkk kkkk ADDWF k Syntax: Operands: ADD W to f [ label ] ADDWF 0 f 255 d [0,1] a [0,1] (WREG) + (f) dest N,OV, C, DC, Z 0010 01da ffff ffff f [,d] [,a] Operation: Status Affected: Encoding: Description: The contents of WREG are added to the 8-bit literal 'k' and the result is placed in WREG. 1 1 Q2 Read literal 'k' ADDLW = = = = = = = = = = = = 0x10 ? ? ? ? ? 0x25 0 0 0 0 0 Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x15 Q4 Write to W Add WREG to register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ADDWF = = = = = = = = = = = = = = 0x17 0xC2 ? ? ? ? ? 0xD9 0xC2 1 0 0 0 0 Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG N OV C DC Z WREG N OV C DC Z Before Instruction Q3 Process Data REG, W Q4 Write to destination Example: WREG REG N OV C DC Z WREG REG N OV C DC Z Before Instruction After Instruction After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 267 PIC18CXX8 ADDWFC Syntax: Operands: ADD WREG and Carry bit to f [ label ] ADDWFC 0 f 255 d [0,1] a [0,1] (WREG) + (f) + (C) dest N,OV, C, DC, Z 0010 00da ffff ffff ANDLW Syntax: Operands: Operation: Status Affected: Encoding: Description: AND literal with WREG [ label ] ANDLW 0 k 255 (WREG) .AND. k WREG N,Z 0000 1011 kkkk kkkk f [ ,d [,a] ] k Operation: Status Affected: Encoding: Description: Add WREG, the Carry Flag and data memory location 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed in data memory location 'f'. If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ADDWFC = = = = = = = 1 0x02 0x4D ? ? ? ? The contents of WREG are AND'ed with the 8-bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' ANDLW = = = = = = 0xA3 ? ? 0x03 0 0 Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x5F Q4 Write to W Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q3 Process Data REG, W Before Instruction Q4 Write to destination WREG N Z WREG N Z After Instruction Example: C REG WREG N OV DC Z Before Instruction After Instruction C REG WREG N OV DC Z = = = = = = = 0 0x02 0x50 0 0 0 0 DS30475A-page 268 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 ANDWF Syntax: Operands: AND WREG with f [ label ] ANDWF 0 f 255 d [0,1] a [0,1] (WREG) .AND. (f) dest N,Z 0001 01da ffff ffff BC f [ ,d [,a] ] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Carry [ label ] BC n -128 n 127 if carry bit is '1' (PC) + 2 + 2n PC None 1110 0010 nnnn nnnn Operation: Status Affected: Encoding: Description: The contents of WREG are AND'ed with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ANDWF = = = = = = = = 0x17 0xC2 ? ? 0x02 0xC2 0 0 If the Carry bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: WREG REG N Z WREG REG N Z Before Instruction If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BC 5 Q4 No operation After Instruction Example: PC Before Instruction address (HERE) 1; address (HERE+12) 0; address (HERE+2) After Instruction If Carry PC If Carry PC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 269 PIC18CXX8 BCF Syntax: Operands: Bit Clear f [ label ] BCF 0 f 255 0b7 a [0,1] 0 f None 1001 bbba ffff ffff BN f, b [,a] Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Negative [ label ] BN n -128 n 127 if negative bit is '1' (PC) + 2 + 2n PC None 1110 0110 nnnn nnnn Operation: Status Affected: Encoding: Description: Bit 'b' in register 'f' is cleared. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' = 1, the Bank will be selected as per the BSR value. 1 1 Words: Q2 Read register 'f' BCF Words: Cycles: Q Cycle Activity: Q1 Decode If the Negative bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Q3 Process Data FLAG_REG, 7 Q4 Write register 'f' Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: Before Instruction FLAG_REG = 0xC7 After Instruction FLAG_REG = 0x47 If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BN Jump Q4 No operation Example: PC Before Instruction address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Negative PC If Negative PC DS30475A-page 270 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 BNC Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Carry [ label ] BNC -128 n 127 if carry bit is '0' (PC) + 2 + 2n PC None 1110 0011 nnnn nnnn BNN Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Negative [ label ] BNN -128 n 127 if negative bit is '0' (PC) + 2 + 2n PC None 1110 0111 nnnn nnnn n n If the Carry bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Negative bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BNC Jump Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE = Q3 Process Data BNN Jump Q4 No operation Example: PC Example: PC Before Instruction address (HERE) 0; address (Jump) 1; address (HERE+2) Before Instruction address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Carry PC If Carry PC After Instruction If Negative PC If Negative PC = = = = 2000 Microchip Technology Inc. Advanced Information DS30475A-page 271 PIC18CXX8 BNOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Overflow [ label ] BNOV -128 n 127 if overflow bit is '0' (PC) + 2 + 2n PC None 1110 0101 nnnn nnnn BNZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Not Zero [ label ] BNZ -128 n 127 if zero bit is '0' (PC) + 2 + 2n PC None 1110 0001 nnnn nnnn n n If the Overflow bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) If the Zero bit is '0', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BNOV Jump address (HERE) 0; address (Jump) 1; address (HERE+2) Q4 No operation If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BNZ Jump Q4 No operation Example: PC Example: PC Before Instruction After Instruction If Overflow PC If Overflow PC Before Instruction address (HERE) 0; address (Jump) 1; address (HERE+2) After Instruction If Zero PC If Zero PC DS30475A-page 272 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 BRA Syntax: Operands: Operation: Status Affected: Encoding: Description: Unconditional Branch [ label ] BRA n -1024 n 1023 (PC) + 2 + 2n PC None 1101 0nnn nnnn nnnn BSF Syntax: Operands: Bit Set f [ label ] BSF 0 f 255 0b7 a [0,1] 1 f None 1000 bbba ffff ffff f, b [,a] Operation: Status Affected: Encoding: Description: Add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a twocycle instruction. 1 2 Q2 Read literal 'n' No operation Words: Cycles: Q Cycle Activity: Q1 Decode No operation Bit 'b' in register 'f' is set. If 'a' is 0 Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value (default). 1 1 Q2 Read register 'f' BSF = = Words: Cycles: Q3 Process Data No operation Q4 Write to PC No operation Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write register 'f' Example: Example: PC HERE = = BRA Jump FLAG_REG, 7, 1 0x0A 0x8A Before Instruction FLAG_REG Before Instruction address (HERE) address (Jump) After Instruction FLAG_REG After Instruction PC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 273 PIC18CXX8 BTFSC Syntax: Operands: Bit Test File, Skip if Clear [ label ] BTFSC f, b [,a] 0 f 255 0b7 a [0,1] skip if (f) = 0 None 1011 bbba ffff ffff BTFSS Syntax: Operands: Bit Test File, Skip if Set [ label ] BTFSS f, b [,a] 0 f 255 0b<7 a [0,1] skip if (f) = 1 None 1010 bbba ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: If bit 'b' in register 'f' is 0, then the next instruction is skipped. If bit 'b' is 0, then the next instruction fetched during the current instruction execution is discarded, and a NOP is executed instead, making this a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' If bit 'b' in register 'f' is 1 then the next instruction is skipped. If bit 'b' is 1, then the next instruction fetched during the current instruction execution, is discarded and an NOP is executed instead, making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSC : : Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE FALSE TRUE = = = = = No operation No operation BTFSS : : Q4 No operation No operation Example: FLAG, 1, ACCESS Example: FLAG, 1, ACCESS Before Instruction PC address (HERE) 0; address (TRUE) 1; address (FALSE) Before Instruction PC address (HERE) 0; address (FALSE) 1; address (TRUE) After Instruction If FLAG<1> PC If FLAG<1> PC After Instruction If FLAG<1> PC If FLAG<1> PC DS30475A-page 274 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 BTG Syntax: Operands: Bit Toggle f [ label ] BTG f, b [,a] 0 f 255 0b<7 a [0,1] (f) f None 0111 bbba ffff ffff BOV Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Overflow [ label ] BOV -128 n 127 if overflow bit is '1' (PC) + 2 + 2n PC None 1110 0100 nnnn nnnn n Operation: Status Affected: Encoding: Description: Bit 'b' in data memory location 'f' is inverted. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Words: Q2 Read register 'f' BTG = = Words: Cycles: Q Cycle Activity: Q1 Decode If the Overflow bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Q3 Process Data PORTC, 4 Q4 Write register 'f' Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Example: PORTC PORTC Before Instruction: 0111 0101 [0x75] 0110 0101 [0x65] After Instruction: If No Jump: Q1 Decode Q2 Read literal 'n' HERE = = = = = Q3 Process Data BOV Jump Q4 No operation Example: PC Before Instruction address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Overflow PC If Overflow PC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 275 PIC18CXX8 BZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Branch if Zero [ label ] BZ n -128 n 127 if Zero bit is '1' (PC) + 2 + 2n PC None 1110 0000 nnnn nnnn CALL Syntax: Operands: Operation: Subroutine Call [ label ] CALL k [,s] 0 k 1048575 s [0,1] (PC) + 4 TOS, k PC<20:1>, if s = 1 (WREG) WS, (STATUS) STATUSS, (BSR) BSRS None 1110 1111 110s k19kkk k7kkk kkkk kkkk0 kkkk8 If the Zero bit is '1', then the program will branch. The 2's complement number '2n' is added to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is then a two-cycle instruction. 1 1(2) Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Words: Cycles: Q Cycle Activity: If Jump: Q1 Decode No operation Q2 Read literal 'n' No operation Q3 Process Data No operation Q4 Write to PC No operation Subroutine call of entire 2M byte memory range. First, return address (PC+ 4) is pushed onto the return stack. If 's' = 1, the WREG, STATUS and BSR registers are also pushed into their respective shadow registers, WS, STATUSS and BSRS. If 's' = 0, no update occurs (default). Then the 20-bit value 'k' is loaded into PC<20:1>. CALL is a two-cycle instruction. 2 2 Q2 Read literal 'k'<7:0>, No operation HERE = If No Jump: Q1 Decode Words: Q2 Read literal 'n' HERE = = = = = Q3 Process Data BZ Jump Q4 No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Push PC to stack No operation CALL Q4 Read literal 'k'<19:8>, Write to PC No operation Example: PC Before Instruction address (HERE) 1; address (Jump) 0; address (HERE+2) After Instruction If Zero PC If Zero PC No operation Example: PC THERE, FAST Before Instruction Address(HERE) Address(THERE) Address (HERE + 4) WREG BSR STATUS After Instruction PC = TOS = WS = BSRS = STATUSS = DS30475A-page 276 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 CLRF Syntax: Operands: Operation: Status Affected: Encoding: Description: Clear f [label] CLRF 0 f 255 a [0,1] 000h f 1Z Z 0110 101a ffff ffff CLRWDT f [,a] Syntax: Operands: Operation: Clear Watchdog Timer [ label ] CLRWDT None 000h WDT, 000h WDT postscaler, 1 TO, 1 PD TO, PD 0000 0000 0000 0100 Status Affected: Encoding: Description: Clears the contents of the specified register. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' CLRF = = = = 0x5A ? 0x00 0 CLRWDT instruction resets the Watchdog Timer. It also resets the postscaler of the WDT. Status bits TO and PD are set. 1 1 Q2 No operation CLRWDT = = = = = = = = ? ? ? ? 0x00 0 1 1 Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q3 Process Data FLAG_REG Q4 Write register 'f' Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Example: Example: Before Instruction FLAG_REG Z Before Instruction WDT counter WDT postscaler After Instruction FLAG_REG Z TO PD After Instruction WDT counter WDT postscaler TO PD 2000 Microchip Technology Inc. Advanced Information DS30475A-page 277 PIC18CXX8 COMF Syntax: Operands: Complement f [ label ] COMF 0 f 255 d [0,1] a [0,1] ( f ) dest N,Z 0001 11da ffff ffff CPFSEQ f [ ,d [,a] ] Syntax: Operands: Operation: Compare f with WREG, skip if f = WREG [ label ] CPFSEQ 0 f 255 a [0,1] (f) - (WREG), skip if (f) = (WREG) (unsigned comparison) None 0110 001a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The contents of register 'f' are complemented. If 'd' is 0 the result is stored in W. If 'd' is 1 the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If 'f' = WREG, then the fetched instruction is discarded and an NOP is executed instead making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Q3 Process Data Q4 Write to destination Words: Cycles: Example: REG N Z REG WREG N Z = = = = = = = COMF 0x13 ? ? 0x13 0xEC 1 0 REG Before Instruction Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation If skip: Q1 No operation After Instruction Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NEQUAL EQUAL No operation No operation CPFSEQ REG : : HERE ? ? WREG; Address (EQUAL) WREG; Address (NEQUAL) Q4 No operation No operation Example: Before Instruction PC Address = WREG = REG = After Instruction If REG = PC = If REG PC = DS30475A-page 278 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 CPFSGT Syntax: Operands: Operation: Compare f with WREG, skip if f > WREG [ label ] CPFSGT 0 f 255 a [0,1] (f) - (WREG), skip if (f) > (WREG) (unsigned comparison) None 0110 010a ffff ffff CPFSLT Syntax: Operands: Operation: Compare f with WREG, skip if f < WREG [ label ] CPFSLT 0 f 255 a [0,1] (f) - (WREG), skip if (f) < (WREG) (unsigned comparison) None 0110 000a ffff ffff f [,a] f [,a] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Compares the contents of data memory location 'f' to the contents of the WREG by performing an unsigned subtraction. If the contents of 'f' are greater than the contents of , then the fetched instruction is discarded and a NOP is executed instead making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note:3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Compares the contents of data memory location 'f' to the contents of W by performing an unsigned subtraction. If the contents of 'f' are less than the contents of WREG, then the fetched instruction is discarded and a NOP is executed instead making this a two-cycle instruction. If 'a' is 0, the Access Bank will be selected. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation Q3 Process Data Q4 No operation If skip: Q1 Q2 No operation If skip: Q1 No operation Q3 No operation Q4 No operation Q2 No operation Q3 No operation Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NGREATER GREATER No operation No operation CPFSGT REG : : If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NLESS LESS = = < = = No operation No operation CPFSLT REG : : Address (HERE) ? WREG; Address (LESS) WREG; Address (NLESS) Q4 No operation No operation Q4 No operation No operation Example: Example: Before Instruction PC WREG Before Instruction PC = WREG = After Instruction If REG > PC = If REG PC = Address (HERE) ? WREG; Address (GREATER) WREG; Address (NGREATER) After Instruction If REG PC If REG PC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 279 PIC18CXX8 DAW Syntax: Operands: Operation: Decimal Adjust WREG Register [label] DAW None If [WREG<3:0> >9] or [DC = 1] then (WREG<3:0>) + 6 W<3:0>; else (WREG<3:0>) W<3:0>; If [WREG<7:4> >9] or [C = 1] then DECF Syntax: Operands: Decrement f [ label ] DECF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) - 1 dest C,DC,N,OV,Z 0000 01da ffff ffff Operation: Status Affected: Encoding: Description: (WREG<7:4>) + 6 WREG<7:4>; else (WREG<7:4>) WREG<7:4>; Status Affected: Encoding: Description: C 0000 0000 0000 0111 DAW adjusts the eight bit value in WREG resulting from the earlier addition of two variables (each in packed BCD format) and produces a correct packed BCD result. 1 1 Q2 Q3 Process Data Decrement register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' DECF = = = = 0x01 0 0x00 1 Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT Q4 Write to destination Q4 Write WREG Example: CNT Z CNT Z Read register WREG DAW = = = = = = 0xA5 0 0 0x05 1 0 Before Instruction Example1: WREG C DC WREG C DC Before Instruction After Instruction After Instruction Example 2: Before Instruction WREG C DC WREG C DC = = = = = = 0xCE 0 0 0x34 1 0 After Instruction DS30475A-page 280 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 DECFSZ Syntax: Operands: Decrement f, skip if 0 [ label ] DECFSZ f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result = 0 None 0010 11da ffff ffff DCFSNZ Syntax: Operands: Decrement f, skip if not 0 [label] DCFSNZ f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) - 1 dest, skip if result 0 None 0100 11da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are decremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are decremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead making it a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE CONTINUE No operation No operation DECFSZ GOTO Q4 No operation No operation CNT LOOP If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO = = = = = No operation No operation DCFSNZ : : ? TEMP Q4 No operation No operation Example: Example: Before Instruction PC CNT If CNT PC If CNT PC = = = = = Address (HERE) CNT - 1 0; Address (CONTINUE) 0; Address (HERE+2) Before Instruction TEMP After Instruction After Instruction TEMP If TEMP PC If TEMP PC TEMP - 1, 0; Address (ZERO) 0; Address (NZERO) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 281 PIC18CXX8 GOTO Syntax: Operands: Operation: Status Affected: Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: Unconditional Branch [ label ] GOTO k 0 k 1048575 k PC<20:1> None 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 INCF Syntax: Operands: Increment f [ label ] INCF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) + 1 dest C,DC,N,OV,Z 0010 10da ffff ffff Operation: Status Affected: Encoding: Description: GOTO allows an unconditional branch anywhere within entire 2M byte memory range. The 20-bit value 'k' is loaded into PC<20:1>. GOTO is always a two-cycle instruction. 2 2 Words: Cycles: Q Cycle Activity: Q1 Decode The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' INCF = = = = = = = = 0xFF 0 ? ? 0x00 1 1 1 Words: Q2 Read literal 'k'<7:0>, No operation Q3 No operation No operation Q4 Read literal 'k'<19:8>, Write to PC No operation Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data CNT Q4 Write to destination No operation Example: PC = GOTO THERE Address (THERE) Example: CNT Z C DC CNT Z C DC After Instruction Before Instruction After Instruction DS30475A-page 282 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 INCFSZ Syntax: Operands: Increment f, skip if 0 [ label ] INCFSZ f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result = 0 None 0011 11da ffff ffff INFSNZ Syntax: Operands: Increment f, skip if not 0 [label] INFSNZ f [, d [,a] ] 0 f 255 d [0,1] a [0,1] (f) + 1 dest, skip if result 0 None 0100 10da ffff ffff Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead making it a two-cycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' The contents of register 'f' are incremented. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If the result is not 0, the next instruction, which is already fetched, is discarded, and a NOP is executed instead making it a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction. Q2 Read register 'f' Words: Cycles: Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination If skip: Q1 No operation If skip: Q2 No operation Q3 No operation Q4 No operation Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO = = = = = No operation No operation INCFSZ : : CNT Q4 No operation No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE ZERO NZERO = = No operation No operation INFSNZ REG Q4 No operation No operation Example: Example: Before Instruction PC CNT If CNT PC If CNT PC Address (HERE) CNT + 1 0; Address(ZERO) 0; Address(NZERO) Before Instruction PC REG If REG PC If REG PC Address (HERE) REG + 1 0; Address (NZERO) 0; Address (ZERO) After Instruction After Instruction = = = 2000 Microchip Technology Inc. Advanced Information DS30475A-page 283 PIC18CXX8 IORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Inclusive OR literal with WREG [ label ] IORLW k 0 k 255 (WREG) .OR. k WREG N,Z 0000 1001 kkkk kkkk IORWF Syntax: Operands: Inclusive OR WREG with f [ label ] IORWF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (WREG) .OR. (f) dest N,Z 0001 00da ffff ffff Operation: Status Affected: Encoding: Description: The contents of WREG are OR'ed with the eight bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' IORLW = = = = = = 0x9A ? ? 0xBF 1 0 Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data 0x35 Q4 Write to W Inclusive OR W with register 'f'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' IORWF = = = = = = = = 0x13 0x91 ? ? 0x13 0x93 1 0 Words: Example: WREG N Z WREG N Z Cycles: Q Cycle Activity: Q1 Decode Before Instruction Q3 Process Data RESULT, W Q4 Write to destination After Instruction Example: RESULT WREG N Z RESULT WREG N Z Before Instruction After Instruction DS30475A-page 284 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 LFSR Syntax: Operands: Operation: Status Affected: Encoding: Description: Load FSR [ label ] LFSR f,k 0f2 0 k 4095 k FSRf None 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk MOVF Syntax: Operands: Move f [ label ] MOVF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] f dest N,Z 0101 00da ffff ffff Operation: Status Affected: Encoding: Description: The 12-bit literal 'k' is loaded into the file select register pointed to by 'f' 2 2 Q2 Read literal 'k' MSB Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write literal 'k' MSB to FSRfH Write literal 'k' to FSRfL The contents of register 'f' is moved to a destination dependent upon the status of 'd'. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). Location 'f' can be anywhere in the 256 byte Bank. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' MOVF = = = = = = = = Decode Read literal 'k' LSB Process Data Words: Cycles: Q Cycle Activity: Q1 Decode Example: FSR2H FSR2L LFSR FSR2, 0x3AB = = 0x03 0xAB Q3 Process Data REG, W 0x22 0xFF ? ? 0x22 0x22 0 0 Q4 Write W After Instruction Example: REG WREG N Z Before Instruction After Instruction REG WREG N Z 2000 Microchip Technology Inc. Advanced Information DS30475A-page 285 PIC18CXX8 MOVFF Syntax: Operands: Operation: Status Affected: Encoding: 1st word (source) 2nd word (destin.) Description: Move f to f [label] MOVFF fs,fd 0 fs 4095 0 fd 4095 (fs) fd None 1100 1111 ffff ffff ffff ffff ffffs ffffd MOVLB Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to low nibble in BSR [ label ] k BSR None 0000 0001 kkkk kkkk MOVLB k 0 k 255 The 8-bit literal 'k' is loaded into the Bank Select Register (BSR). 1 1 Q2 Read literal 'k' The contents of source register 'fs' are moved to destination register 'fd'. Location of source 'fs' can be anywhere in the 4096 byte data space (000h to FFFh), and location of destination 'fd' can also be anywhere from 000h to FFFh. Either source or destination can be WREG (a useful special situation). MOVFF is particularly useful for transferring a data memory location to a peripheral register (such as the transmit buffer or an I/O port). The MOVFF instruction cannot use the PCL, TOSU, TOSH or TOSL as the destination register. Q3 Process Data Q4 Write literal 'k' to BSR Example: MOVLB = = 0x05 0x02 0x05 Before Instruction BSR register After Instruction BSR register Words: Cycles: Q Cycle Activity: Q1 Decode 2 2 (3) Q2 Read register 'f' (src) No operation No dummy read Q3 Process Data No operation Q4 No operation Write register 'f' (dest) Decode Example: REG1 REG2 MOVFF = = = = REG1, REG2 0x33 0x11 0x33, 0x33 Before Instruction After Instruction REG1 REG2 DS30475A-page 286 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 MOVLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Move literal to WREG [ label ] MOVLW k 0 k 255 k WREG None 0000 1110 kkkk kkkk MOVWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Move WREG to f [ label ] MOVWF f [,a] 0 f 255 a [0,1] (WREG) f None 0110 111a ffff ffff The eight bit literal 'k' is loaded into WREG. 1 1 Q2 Read literal 'k' MOVLW = 0x5A Q3 Process Data 0x5A Q4 Write to W Move data from WREG to register 'f'. Location 'f' can be anywhere in the 256 byte Bank. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' MOVWF = = = = 0x4F 0xFF 0x4F 0x4F Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG After Instruction Q3 Process Data REG Q4 Write register 'f' Example: WREG REG WREG REG Before Instruction After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 287 PIC18CXX8 MULLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply Literal with WREG [ label ] MULLW k 0 k 255 (WREG) x k PRODH:PRODL None 0000 1101 kkkk kkkk MULWF Syntax: Operands: Operation: Status Affected: Encoding: Description: Multiply WREG with f [ label ] MULWF f [,a] 0 f 255 a [0,1] (WREG) x (f) PRODH:PRODL None 0000 001a ffff ffff An unsigned multiplication is carried out between the contents of WREG and the 8-bit literal 'k'. The 16-bit result is placed in PRODH:PRODL register pair. PRODH contains the high byte. WREG is unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. 1 1 Q2 Read literal 'k' Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write registers PRODH: PRODL An unsigned multiplication is carried out between the contents of WREG and the register file location 'f'. The 16-bit result is stored in the PRODH:PRODL register pair. PRODH contains the high byte. Both WREG and 'f' are unchanged. None of the status flags are affected. Note that neither overflow nor carry is possible in this operation. A zero result is possible but not detected. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode Example: WREG PRODH PRODL MULLW = = = = = = 0xC4 0xE2 ? ? 0xE2 0xAD 0x08 Before Instruction Q3 Process Data Q4 Write registers PRODH: PRODL After Instruction WREG PRODH PRODL Example: WREG REG PRODH PRODL MULWF = = = = = = = = REG 0xC4 0xB5 ? ? 0xC4 0xB5 0x8A 0x94 Before Instruction After Instruction WREG REG PRODH PRODL DS30475A-page 288 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 NEGF Syntax: Operands: Operation: Status Affected: Encoding: Description: Negate f [label] NEGF f [,a] 0 f 255 a [0,1] (f)+1f N,OV, C, DC, Z 0110 110a ffff ffff NOP Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode No Operation [ label ] None No operation None 0000 1111 0000 xxxx 0000 xxxx 0000 xxxx NOP Location 'f' is negated using two's complement. The result is placed in the data memory location 'f'. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' NEGF = = = = = = = = = = = = No operation. 1 1 Q2 No operation Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Q3 Process Data REG Q4 Write register 'f' None. Example: REG N OV C DC Z REG N OV C DC Z Before Instruction 0011 1010 [0x3A] ? ? ? ? ? 1100 0110 [0xC6] 1 0 0 0 0 After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 289 PIC18CXX8 POP Syntax: Operands: Operation: Status Affected: Encoding: Description: Pop Top of Return Stack [ label ] None (TOS) bit bucket None 0000 0000 0000 0110 PUSH Syntax: Operands: Operation: Status Affected: Encoding: Description: Push Top of Return Stack [ label ] None (PC+2) TOS None 0000 0000 0000 0101 POP PUSH The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack. This instruction is provided to enable the user to properly manage the return stack to incorporate a software stack. 1 1 Q2 No operation POP GOTO The PC+2 is pushed onto the top of the return stack. The previous TOS value is pushed down on the stack. This instruction allows implementing a software stack by modifying TOS, and then push it onto the return stack. 1 1 Q2 Push PC+2 onto return stack PUSH = = 00345Ah 000124h Words: Cycles: Q Cycle Activity: Q1 Decode Words: Cycles: Q Cycle Activity: Q1 Decode Q3 No operation Q4 No operation Q3 Pop TOS value Q4 No operation Example: Example: NEW = = 0031A2h 014332h TOS PC Before Instruction Before Instruction TOS Stack (1 level down) After Instruction PC TOS Stack (1 level down) = = = 000126h 000126h 00345Ah After Instruction TOS PC = = 014332h NEW DS30475A-page 290 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 RCALL Syntax: Operands: Operation: Status Affected: Encoding: Description: Relative Call [ label ] RCALL -1024 n 1023 (PC) + 2 TOS, (PC) + 2 + 2n PC None 1101 1nnn nnnn nnnn RESET n Syntax: Operands: Operation: Status Affected: Encoding: Description: Words: Cycles: Q Cycle Activity: Q1 Decode Reset [ label ] None Reset all registers and flags that are affected by a MCLR Reset. All 0000 0000 1111 1111 RESET Subroutine call with a jump up to 1K from the current location. First, return address (PC+2) is pushed onto the stack. Then, add the 2's complement number '2n' to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC+2+2n. This instruction is a two-cycle instruction. 1 2 Q2 Read literal 'n' Push PC to stack This instruction provides a way to execute a MCLR Reset in software. 1 1 Q2 Start reset RESET Reset Value Reset Value Q3 No operation Q4 No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: Registers = Flags* = After Instruction Q3 Process Data Q4 Write to PC No operation No operation HERE No operation RCALL Jump No operation Example: PC = PC = TOS = Before Instruction Address(HERE) Address(Jump) Address (HERE+2) After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 291 PIC18CXX8 RETFIE Syntax: Operands: Operation: Return from Interrupt [ label ] s [0,1] (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged. None 0000 0000 0001 000s RETLW Syntax: Operands: Operation: Return Literal to WREG [ label ] RETLW k 0 k 255 k W, (TOS) PC, PCLATU, PCLATH are unchanged None 0000 1100 kkkk kkkk RETFIE [s] Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from Interrupt. Stack is popped and Top-of-Stack (TOS) is loaded into the PC. Interrupts are enabled by setting the either the high or low priority global interrupt enable bit. If 's' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, WREG, STATUS and BSR. If 's' = 0, no update of these registers occurs (default). 1 2 W is loaded with the eight bit literal 'k'. The program counter is loaded from the top of the stack (the return address). The high address latch (PCLATH) remains unchanged. 1 2 Q2 Read literal 'k' No operation Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data No operation Q4 Pop PC from stack, write to W No operation No operation Words: Cycles: Q Cycle Activity: Q1 Decode Example: CALL TABLE ; WREG contains table ; offset value ; WREG now has ; table value Q2 No operation Q3 No operation Q4 Pop PC from stack Set GIEH or GIEL : TABLE ADDWF RETLW RETLW : : RETLW No operation No operation RETFIE 1 No operation No operation PCL k0 k1 ; WREG = offset ; Begin table ; Example: After Interrupt kn ; End of table PC WREG BSR STATUS GIE/GIEH, PEIE/GIEL = = = = = TOS WS BSRS STATUSS 1 Before Instruction WREG WREG = = 0x07 value of kn After Instruction DS30475A-page 292 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 RETURN Syntax: Operands: Operation: Return from Subroutine [ label ] s [0,1] (TOS) PC, if s = 1 (WS) W, (STATUSS) STATUS, (BSRS) BSR, PCLATU, PCLATH are unchanged None 0000 0000 0001 001s RLCF Syntax: Operands: Rotate Left f through Carry [ label ] RLCF 0 f 255 d [0,1] a [0,1] (f 0011 01da ffff ffff RETURN [s] f [ ,d [,a] ] Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: Return from subroutine. The stack is popped and the top of the stack (TOS) is loaded into the program counter. If 's' = 1, the contents of the shadow registers WS, STATUSS and BSRS are loaded into their corresponding registers, WREG, STATUS and BSR. If 's' = 0, no update of these registers occurs (default). 1 2 Q2 No operation No operation The contents of register 'f' are rotated one bit to the left through the Carry Flag. If 'd' is 0 the result is placed in WREG. If 'd' is 1 the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. C register f Words: Cycles: Q Cycle Activity: Q1 Decode No operation Words: Cycles: Q3 Process Data No operation 1 1 Q2 Read register 'f' RLCF = = = = = = = = = Q4 Pop PC from stack No operation Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: Example: After Call PC = TOS RETURN FAST RETURN REG C N Z REG WREG C N Z Before Instruction 1110 0110 0 ? ? 1110 0110 1100 1100 1 1 0 Before Instruction WRG = STATUS = BSR = 0x04 0x00 0x00 0x04 0x00 0x00 TOS After Instruction After Instruction WREG STATUS BSR PC = = = = 2000 Microchip Technology Inc. Advanced Information DS30475A-page 293 PIC18CXX8 RLNCF Syntax: Operands: Rotate Left f (no carry) [ label ] RLNCF 0 f 255 d [0,1] a [0,1] (f 0100 01da ffff ffff RRCF Syntax: Operands: Rotate Right f through Carry [ label ] RRCF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f 0011 00da ffff ffff f [ ,d [,a] ] Operation: Status Affected: Encoding: Description: Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the left. If 'd' is 0 the result is placed in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. register f The contents of register 'f' are rotated one bit to the right through the Carry Flag. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. C register f Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Words: Q2 Read register 'f' RLNCF = = = 1 1 Q2 Read register 'f' RRCF = = = = = = = = = Q3 Process Data REG Q4 Write to destination Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG, W Q4 Write to destination Example: REG N Z Before Instruction 1010 1011 ? ? Example: REG C N Z REG WREG C N Z Before Instruction 1110 0110 0 ? ? 1110 0110 0111 0011 0 0 0 After Instruction REG N Z = = = 0101 0111 0 0 After Instruction DS30475A-page 294 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 RRNCF Syntax: Operands: Rotate Right f (no carry) [ label ] RRNCF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f 0100 00da ffff ffff SETF Syntax: Operands: Operation: Status Affected: Encoding: Description: Set f [label] SETF 0 f 255 a [0,1] FFh f None 0110 100a ffff ffff f [,a] Operation: Status Affected: Encoding: Description: The contents of register 'f' are rotated one bit to the right. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. register f The contents of the specified register are set to FFh. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' SETF = = 0x5A 0xFF Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write register 'f' Words: Cycles: Q Cycle Activity: Q1 Decode 1 1 Q2 Read register 'f' RRNCF = = = = = = Example: Q3 Process Data REG Before Instruction Q4 Write to destination REG After Instruction REG Example 1: REG N Z REG N Z Before Instruction 1101 0111 ? ? 1110 1011 1 0 RRNCF = = = = = = = = REG, 0, 0 After Instruction Example 2: WREG REG N Z WREG REG N Z Before Instruction ? 1101 0111 ? ? 1110 1011 1101 0111 1 0 After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 295 PIC18CXX8 SLEEP Syntax: Operands: Operation: Enter SLEEP mode [ label ] SLEEP None 00h WDT, 0 WDT postscaler, 1 TO, 0 PD TO, PD 0000 0000 0000 0011 SUBFWB Syntax: Operands: Subtract f from WREG with borrow [ label ] SUBFWB f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (WREG) - (f) - (C) dest N,OV, C, DC, Z 0101 01da ffff ffff Operation: Status Affected: Encoding: Description: Status Affected: Encoding: Description: The power-down status bit (PD) is cleared. The time-out status bit (TO) is set. Watchdog Timer and its postscaler are cleared. The processor is put into SLEEP mode with the oscillator stopped. 1 1 Words: Q2 No operation SLEEP ? ? 1 0 Words: Cycles: Q Cycle Activity: Q1 Decode Subtract register 'f' and carry flag (borrow) from WREG (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored in register 'f' (default) . If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' Q3 Process Data Q4 Go to sleep Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data Q4 Write to destination Example: TO = PD = TO = PD = Before Instruction After Instruction If WDT causes wake-up, this bit is cleared. DS30475A-page 296 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 SUBFWB (Cont.) Example 1: REG WREG C REG WREG C Z N = = = = = = = = SUBLW SUBFWB 3 2 1 0xFF 2 0 0 1 ; result is negative SUBFWB = = = = = = = = 2 5 1 2 3 1 0 0 REG REG Subtract WREG from literal [ label ] SUBLW k 0 k 255 k - (WREG) WREG N,OV, C, DC, Z 0000 1000 kkkk kkkk Syntax: Operands: Operation: Status Affected: Encoding: Description: Before Instruction After Instruction WREG is subtracted from the eight bit literal 'k'. The result is placed in WREG. 1 1 Q2 Read literal 'k' SUBLW = = = = = = 1 ? 1 1 0 0 SUBLW = = = = = = 2 ? 0 1 1 0 SUBLW = = = = = = 3 ? 0xFF ; (2's complement) 0 ; result is negative 0 1 Words: Cycles: Q Cycle Activity: Q1 Decode Example 2: REG WREG C REG WREG C Z N Before Instruction Q3 Process Data 0x02 Q4 Write to W After Instruction Example 1: WREG C ; result is positive REG WREG C Z N Before Instruction After Instruction ; result is positive Example 3: REG WREG C REG WREG C Z N = = = = = = = = SUBFWB 1 2 0 0 2 1 1 0 Before Instruction After Instruction Example 2: WREG C ; result is zero WREG C Z N 0x02 Before Instruction After Instruction ; result is zero Example 3: WREG C WREG C Z N 0x02 Before Instruction After Instruction 2000 Microchip Technology Inc. Advanced Information DS30475A-page 297 PIC18CXX8 SUBWF Syntax: Operands: Subtract WREG from f [ label ] SUBWF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) - (WREG) dest N,OV, C, DC, Z 0101 11da ffff ffff SUBWF Example 1: REG WREG C REG WREG C Z N = = = = = = = = Subtract WREG from f (cont'd) SUBWF 3 2 ? 1 2 1 0 0 SUBWF = = = = = = = = 2 2 ? 2 0 1 1 0 SUBWF = = = = = = = = 1 2 ? 0xFF ;(2's complement) 2 0 ; result is negative 0 1 REG Before Instruction Operation: Status Affected: Encoding: Description: After Instruction Subtract WREG from register 'f' (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ; result is positive Example 2: REG WREG C REG WREG C Z N REG, W Before Instruction After Instruction Words: Cycles: Q Cycle Activity: Q1 Decode ; result is zero Q3 Process Data Q4 Write to destination Example 3: REG WREG C REG WREG C Z N REG Before Instruction After Instruction DS30475A-page 298 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 SUBWFB Syntax: Operands: Subtract WREG from f with Borrow [ label ] SUBWFB f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f) - (WREG) - (C) dest N,OV, C, DC, Z 0101 10da ffff ffff SUBWFB Example 1: REG WREG C REG WREG C Z N = = = = = = = = Subtract WREG from f with Borrow (cont'd) SUBWFB 0x19 0x0D 1 0x0C 0x0D 1 0 0 SUBWFB = = = = = = = = 0x1B 0x1A 0 0x1B 0x00 1 1 0 SUBWFB = = = = = = = = 0x03 0x0E 1 0xF5 0x0E 0 0 1 REG (0001 1001) (0000 1101) Before Instruction Operation: Status Affected: Encoding: Description: After Instruction (0000 1011) (0000 1101) Subtract WREG and the carry flag (borrow) from register 'f' (2's complement method). If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' ; result is positive REG, W (0001 1011) (0001 1010) Example 2: Before Instruction REG WREG C REG WREG C Z N After Instruction (0001 1011) Words: Cycles: Q Cycle Activity: Q1 Decode ; result is zero Q3 Process Data Q4 Write to destination Example 3: Before Instruction REG WREG C REG WREG C Z N REG (0000 0011) (0000 1101) After Instruction (1111 0100) [2's comp] (0000 1101) ; result is negative 2000 Microchip Technology Inc. Advanced Information DS30475A-page 299 PIC18CXX8 SWAPF Syntax: Operands: Swap nibbles in f [ label ] SWAPF f [ ,d [,a] ] 0 f 255 d [0,1] a [0,1] (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> None 0011 10da ffff ffff Operation: Status Affected: Encoding: Description: The upper and lower nibbles of register 'f' are exchanged. If 'd' is 0, the result is placed in WREG. If 'd' is 1, the result is placed in register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q2 Read register 'f' SWAPF = = 0x53 0x35 Words: Cycles: Q Cycle Activity: Q1 Decode Q3 Process Data REG Q4 Write to destination Example: REG REG Before Instruction After Instruction DS30475A-page 300 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TBLRD Syntax: Operands: Operation: Table Read [ label ] None if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR - No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) +1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) -1 TBLPTR; if TBLRD +*, (TBLPTR) +1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; 0000 0000 0000 10nn nn=0 * =1 *+ =2 *=3 +* TBLRD Example 1: Table Read (cont'd) TBLRD *+ ; = = = = = TBLRD +* ; = = = = = = 0xAA 0x01A357 0x12 0x34 0x34 0x01A358 0x55 0x00A356 0x34 0x34 0x00A357 TBLRD ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(0x00A356) After Instruction TABLAT TBLPTR Example 2: Before Instruction TABLAT TBLPTR MEMORY(0x01A357) MEMORY(0x01A358) Status Affected: None Encoding: After Instruction TABLAT TBLPTR Description: This instruction is used to read the contents of Program Memory (P.M.). To address the program memory, a pointer called Table Pointer (TBLPTR) is used. The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 Mbyte address range. TBLPTR[0] = 0: Least Significant Byte of Program Memory Word TBLPTR[0] = 1: Most Significant Byte of Program Memory Word The TBLRD instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 Q2 No operation No operation (Read Program Memory) Q3 No operation No operation Q4 No operation No operation (Write TABLAT) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 301 PIC18CXX8 TBLWT Syntax: Operands: Operation: Table Write [ label ] None if TBLWT*, (TABLAT) Prog Mem (TBLPTR) or Holding Register; TBLPTR - No Change; if TBLWT*+, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) +1 TBLPTR; if TBLWT*-, (TABLAT) Prog Mem (TBLPTR) or Holding Register; (TBLPTR) -1 TBLPTR; if TBLWT+*, (TBLPTR) +1 TBLPTR; (TABLAT) Prog Mem (TBLPTR) or Holding Register; None 0000 0000 0000 11nn nn=0 * =1 *+ =2 *=3 +* TBLWT Example 1: Table Write (Continued) TBLWT *+; = = = = = = +*; = = = = = = = = 0x34 0x01389A 0xFF 0xFF 0x34 0x01389B 0xFF 0x34 0x55 0x00A356 0xFF 0x55 0x00A357 0x55 TBLWT ( *; *+; *-; +*) Before Instruction TABLAT TBLPTR MEMORY(0x00A356) TABLAT TBLPTR MEMORY(0x00A356) After Instructions (table write completion) Example 2: TBLWT Before Instruction TABLAT TBLPTR MEMORY(0x01389A) MEMORY(0x01389B) TABLAT TBLPTR MEMORY(0x01389A) MEMORY(0x01389B) After Instruction (table write completion) Status Affected: Encoding: Description: This instruction is used to program the contents of Program Memory (P.M.). The TBLPTR (a 21-bit pointer) points to each byte in the program memory. TBLPTR has a 2 MBtye address range. The LSb of the TBLPTR selects which byte of the program memory location to access. TBLPTR[0] = 0:Least Significant Byte of Program Memory Word TBLPTR[0] = 1:Most Significant Byte of Program Memory Word The TBLWT instruction can modify the value of TBLPTR as follows: * no change * post-increment * post-decrement * pre-increment Words: Cycles: Q Cycle Activity: Q1 Decode No operation 1 2 (many if long write is to on-chip EPROM program memory) Q2 No operation No operation (Read TABLAT) Q3 No operation No operation Q4 No operation No operation (Write to Holding Register or Memory) DS30475A-page 302 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TSTFSZ Syntax: Operands: Operation: Status Affected: Encoding: Description: Test f, skip if 0 [ label ] TSTFSZ f [,a] 0 f 255 a [0,1] skip if f = 0 None 0110 011a ffff ffff XORLW Syntax: Operands: Operation: Status Affected: Encoding: Description: Exclusive OR literal with WREG [ label ] XORLW k 0 k 255 (WREG) .XOR. k WREG N,Z 0000 1010 kkkk kkkk If 'f' = 0, the next instruction, fetched during the current instruction execution, is discarded and a NOP is executed making this a twocycle instruction. If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1(2) Note: 3 cycles if skip and followed by a 2-word instruction Q2 Read register 'f' The contents of WREG are XOR'ed with the 8-bit literal 'k'. The result is placed in WREG. 1 1 Q3 Process Data Words: Cycles: Q Cycle Activity: Q1 Q2 Decode Read literal 'k' Q4 Write to WREG Words: Cycles: Example: WREG N Z WREG N Z = = = = = = XORLW 0xAF 0xB5 ? ? 0x1A 0 0 Before Instruction Q Cycle Activity: Q1 Decode Q3 Process Data Q4 No operation After Instruction If skip: Q1 No operation Q2 No operation Q3 No operation Q4 No operation If skip and followed by 2-word instruction: Q1 Q2 Q3 No operation No operation No operation No operation HERE NZERO ZERO = = = = No operation No operation TSTFSZ : : CNT Q4 No operation No operation Example: Before Instruction PC Address (HERE) 0x00, Address (ZERO) 0x00, Address (NZERO) After Instruction If CNT PC If CNT PC 2000 Microchip Technology Inc. Advanced Information DS30475A-page 303 PIC18CXX8 XORWF Syntax: Operands: Exclusive OR WREG with f [ label ] XORWF 0 f 255 d [0,1] a [0,1] (WREG) .XOR. (f) dest N,Z 0001 10da ffff ffff f [ ,d [,a] ] Operation: Status Affected: Encoding: Description: Exclusive OR the contents of WREG with register 'f'. If 'd' is 0, the result is stored in WREG. If 'd' is 1, the result is stored back in the register 'f' (default). If 'a' is 0, the Access Bank will be selected, overriding the BSR value. If 'a' is 1, the Bank will be selected as per the BSR value. 1 1 Q3 Process Data Words: Cycles: Q Cycle Activity: Q1 Q2 Decode Read register 'f' Q4 Write to destination Example: REG WREG N Z REG WREG N Z = = = = = = = = XORWF 0xAF 0xB5 ? ? 0x1A 0xB5 0 0 REG Before Instruction After Instruction DS30475A-page 304 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 24.0 DEVELOPMENT SUPPORT The MPLAB IDE allows you to: * Edit your source files (either assembly or `C') * One touch assemble (or compile) and download to PICmicro tools (automatically updates all project information) * Debug using: - source files - absolute listing file - object code The ability to use MPLAB IDE with Microchip's MPLAB SIM simulator, allows a consistent platform and the ability to easily switch from the cost effective simulator to the full featured emulator with minimal retraining. The microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C17 and MPLAB C18 C Compilers - MPLINKTM Linker/MPLIBTM Librarian * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - ICEPICTM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD for PIC16F877 * Device Programmers - PRO MATE(R) II Universal Device Programmer - PICSTART(R) Plus Entry-Level Development Programmer * Low Cost Demonstration Boards - PICDEMTM 1 Demonstration Board - PICDEM 2 Demonstration Board - PICDEM 3 Demonstration Board - PICDEM 17 Demonstration Board - KEELOQ(R) Demonstration Board PICmicro(R) 24.2 MPASM Assembler The MPASM assembler is a full featured universal macro assembler for all PICmicro MCU's. It can produce absolute code directly in the form of HEX files for device programmers, or it can generate relocatable objects for the MPLINK object linker. The MPASM assembler has a command line interface and a Windows shell and can be used as a stand-alone application on a Windows 3.x, or greater, system. The MPASM assembler generates relocatable object files, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, an absolute LST file, which contains source lines and generated machine code, and a COD file for debugging. The MPASM assembler features include: * MPASM assembler and MPLINK object linker are integrated into MPLAB IDE projects. * MPASM assembler allows user defined macros to be created for streamlined assembly. * MPASM assembler allows conditional assembly for multi-purpose source files. * MPASM assembler directives allow complete control over the assembly process. 24.1 MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8-bit microcontroller market. The MPLAB IDE is a Windows(R)-based application which contains: * Multiple functionality - editor - simulator - programmer (sold separately) - emulator (sold separately) * A full featured editor * A project manager * Customizable tool bar and key mapping * A status bar * On-line help 24.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI `C' compilers and integrated development environments for Microchip's PIC17CXXX and PIC18CXXX family of microcontrollers, respectively. These compilers provide powerful integration capabilities and ease of use not found with other compilers. For easier source level debugging, the compilers provide symbol information that is compatible with the MPLAB IDE memory display. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 305 PIC18CXX8 24.4 MPLINK Linker/MPLIB Librarian 24.6 The MPLINK object linker is a relocatable linker for the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can link relocatable objects from assembly or C source files, along with pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker. When a routine from a library is called from another source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The MPLIB object librarian manages the creation and modification of library files. The MPLINK object linker features include: * MPLINK object linker works with MPASM assembler and MPLAB C17 and MPLAB C18 C compilers. * MPLINK object linker allows all memory areas to be defined as sections to provide link-time flexibility. The MPLIB object librarian features include: * MPLIB object librarian makes linking easier because single libraries can be included instead of many smaller files. * MPLIB object librarian helps keep code maintainable by grouping related modules together. * MPLIB object librarian commands allow libraries to be created and modules to be added, listed, replaced, deleted or extracted. MPLAB ICE High Performance Universal In-Circuit Emulator with MPLAB IDE The MPLAB ICE universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers (MCUs). Software control of the MPLAB ICE in-circuit emulator is provided by the MPLAB Integrated Development Environment (IDE), which allows editing, "make" and download and source debugging from a single environment. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The universal architecture of the MPLAB ICE in-circuit emulator allows expansion to support new PICmicro microcontrollers. The MPLAB ICE in-circuit emulator system has been designed as a real-time emulation system, with advanced features that are generally found on more expensive development tools. The PC platform and Microsoft(R) Windows 3.x/95/98 environment were chosen to best make these features available to you, the end user. The MPLAB ICE in-circuit emulator is available in two versions: MPLAB ICE 1000 and MPLAB ICE 2000. The MPLAB ICE 1000 is a basic, low cost emulator system with simple trace capabilities. The MPLAB ICE 2000 is a full featured emulator system with enhanced trace, trigger and data monitoring features. Both systems use the same processor modules and will operate across the full operating speed range of the PICmicro MCU. 24.5 MPLAB SIM Software Simulator The MPLAB SIM software simulator allows code development in a PC host environment by simulating the PICmicro series microcontrollers on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a file, or user-defined key press, to any of the pins. The execution can be performed in single step, execute until break, or trace mode. The MPLAB SIM simulator fully supports symbolic debugging using the MPLAB C17 and the MPLAB C18 C compilers and the MPASM assembler. The software simulator offers the flexibility to develop and debug code outside of the laboratory environment, making it an excellent multi-project software development tool. 24.7 ICEPIC In-Circuit Emulator The ICEPIC low cost, in-circuit emulator is a solution for the Microchip Technology PIC16C5X, PIC16C6X, PIC16C7X and PIC16CXXX families of 8-bit OneTime-Programmable (OTP) microcontrollers. The modular system can support different subsets of PIC16C5X or PIC16CXXX products through the use of interchangeable personality modules, or daughter boards. The emulator is capable of emulating without target application circuitry being present. DS30475A-page 306 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 24.8 MPLAB ICD In-Circuit Debugger 24.11 Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PIC16F877 and can be used to develop this and other PICmicro microcontrollers from the PIC16CXXX family. The MPLAB ICD utilizes the incircuit debugging capability built into the PIC16F87X. This feature, along with Microchip's In-Circuit Serial ProgrammingTM protocol, offers cost effective in-circuit FLASH programming and debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by watching variables, single-stepping and setting break points. Running at full speed enables testing hardware in real-time. The MPLAB ICD is also a programmer for the FLASH PIC16F87X family. PICDEM 1 Low Cost PICmicro Demonstration Board 24.9 PRO MATE II Universal Device Programmer The PRO MATE II universal device programmer is a full featured programmer, capable of operating in standalone mode, as well as PC-hosted mode. The PRO MATE II device programmer is CE compliant. The PRO MATE II device programmer has programmable VDD and VPP supplies, which allow it to verify programmed memory at VDD min and VDD max for maximum reliability. It has an LCD display for instructions and error messages, keys to enter commands and a modular detachable socket assembly to support various package types. In stand-alone mode, the PRO MATE II device programmer can read, verify, or program PICmicro devices. It can also set code-protect bits in this mode. The PICDEM 1 demonstration board is a simple board which demonstrates the capabilities of several of Microchip's microcontrollers. The microcontrollers supported are: PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs. The user can program the sample microcontrollers provided with the PICDEM 1 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer, and easily test firmware. The user can also connect the PICDEM 1 demonstration board to the MPLAB ICE incircuit emulator and download the firmware to the emulator for testing. A prototype area is available for the user to build some additional hardware and connect it to the microcontroller socket(s). Some of the features include an RS-232 interface, a potentiometer for simulated analog input, push button switches and eight LEDs connected to PORTB. 24.12 PICDEM 2 Low Cost PIC16CXX Demonstration Board 24.10 PICSTART Plus Entry Level Development Programmer The PICSTART Plus development programmer is an easy-to-use, low cost, prototype programmer. It connects to the PC via one of the COM (RS-232) ports. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus development programmer supports all PICmicro devices with up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus development programmer is CE compliant. The PICDEM 2 demonstration board is a simple demonstration board that supports the PIC16C62, PIC16C64, PIC16C65, PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 2 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 2 demonstration board to test firmware. A prototype area has been provided to the user for adding additional hardware and connecting it to the microcontroller socket(s). Some of the features include a RS-232 interface, push button switches, a potentiometer for simulated analog input, a Serial EEPROM to demonstrate usage of the I2CTM bus and separate headers for connection to an LCD module and a keypad. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 307 PIC18CXX8 24.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board 24.14 PICDEM 17 Demonstration Board The PICDEM 17 demonstration board is an evaluation board that demonstrates the capabilities of several Microchip microcontrollers, including PIC17C752, PIC17C756, PIC17C762 and PIC17C766. All necessary hardware is included to run basic demo programs, which are supplied on a 3.5-inch disk. A programmed sample is included and the user may erase it and program it with the other sample programs using the PRO MATE II device programmer, or the PICSTART Plus development programmer, and easily debug and test the sample code. In addition, the PICDEM 17 demonstration board supports down-loading of programs to and executing out of external FLASH memory on board. The PICDEM 17 demonstration board is also usable with the MPLAB ICE in-circuit emulator, or the PICMASTER emulator and all of the sample programs can be run and modified using either emulator. Additionally, a generous prototype area is available for user hardware. The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs. The user can program the sample microcontrollers provided with the PICDEM 3 demonstration board on a PRO MATE II device programmer, or a PICSTART Plus development programmer with an adapter socket, and easily test firmware. The MPLAB ICE in-circuit emulator may also be used with the PICDEM 3 demonstration board to test firmware. A prototype area has been provided to the user for adding hardware and connecting it to the microcontroller socket(s). Some of the features include an RS-232 interface, push button switches, a potentiometer for simulated analog input, a thermistor and separate headers for connection to an external LCD module and a keypad. Also provided on the PICDEM 3 demonstration board is an LCD panel, with 4 commons and 12 segments, that is capable of displaying time, temperature and day of the week. The PICDEM 3 demonstration board provides an additional RS-232 interface and Windows 3.1 software for showing the demultiplexed LCD signals on a PC. A simple serial interface allows the user to construct a hardware demultiplexer for the LCD signals. 24.15 KEELOQ Evaluation and Programming Tools KEELOQ evaluation and programming tools support Microchip's HCS Secure Data Products. The HCS evaluation kit includes an LCD display to show changing codes, a decoder to decode transmissions and a programming interface to program test transmitters. DS30475A-page 308 Advanced Information 2000 Microchip Technology Inc. 24CXX/ 25CXX/ 93CXX PIC14000 HCSXXX PIC16C5X PIC16C6X PIC16C7X PIC16C8X PIC17C4X PIC16F62X PIC16C7XX PIC16F8XX PIC16C9XX PIC17C7XX PIC12CXXX PIC16CXXX PIC18CXX2 MCRFXXX MCP2510 TABLE 24-1: MPLAB(R) Integrated Development Environment a a a a a a a a a a a a aa aa MPLAB(R) C17 C Compiler Software Tools MPLAB(R) C18 C Compiler MPASMTM Assembler/ MPLINKTM Object Linker a a Programmers Debugger Emulators Demo Boards and Eval Kits 2000 Microchip Technology Inc. aaa aa ** aa aa aa aa aa aa aa aa aa aa aa aa MPLAB(R) ICE In-Circuit Emulator ICEPICTM In-Circuit Emulator a * * a a a a a a a MPLAB(R) ICD In-Circuit Debugger a ** a a PICSTART(R) Plus Entry Level Development Programmer a ** a a a a a a a a a a a a a PRO MATE(R) II Universal Device Programmer a a a a a a a a a a a a a a a a PICDEMTM 1 Demonstration Board a a a a a DEVELOPMENT TOOLS FROM MICROCHIP PICDEMTM 2 Demonstration Board a a a Advanced Information a a PICDEMTM 3 Demonstration Board PICDEMTM 14A Demonstration Board PICDEMTM 17 Demonstration Board a KEELOQ(R) Evaluation Kit aa KEELOQ(R) Transponder Kit microIDTM Programmer's Kit aa 125 kHz microIDTM Developer's Kit 125 kHz Anticollision microIDTM Developer's Kit a 13.56 MHz Anticollision microIDTM Developer's Kit a MCP2510 CAN Developer's Kit PIC18CXX8 a DS30475A-page 309 * Contact the Microchip Technology Inc. web site at www.microchip.com for information on how to use the MPLAB(R) ICD In-Circuit Debugger (DV164001) with PIC16C62, 63, 64, 65, 72, 73, 74, 76, 77. ** Contact Microchip Technology Inc. for availability date. PIC18CXX8 NOTES: DS30475A-page 310 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 25.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings () Ambient temperature under bias.............................................................................................................-55C to +125C Storage temperature .............................................................................................................................. -65C to +150C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4) ......................................... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2) ......................................................................................... 0V to +13.25V Voltage on RA4 with respect to Vss ............................................................................................................... 0V to +8.5V Total power dissipation (Note 1) ...............................................................................................................................1.0W Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin ..............................................................................................................................250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...................................................................................................................... 20 mA Output clamp current, IOK (VO < 0 or VO > VDD) .............................................................................................................. 20 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports (combined) ....................................................................................................200 mA Maximum current sourced by all ports (combined) ...............................................................................................200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - IOH} + {(VDD-VOH) x IOH} + (VOl x IOL) 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100 should be used when applying a "low" level to the MCLR/VPP pin, rather than pulling this pin directly to VSS. NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 311 PIC18CXX8 FIGURE 25-1: PIC18CXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V 5.0 V PIC18CXX8 4.2V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 40 MHz Frequency FIGURE 25-2: PIC18LCXX8 VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0 V 5.5 V 5.0 V PIC18LCXX8 4.2V Voltage 4.5 V 4.0 V 3.5 V 3.0 V 2.5 V 2.0 V 6 MHz 40 MHz Frequency FMAX = (20.0 MHz/V) (VDDAPPMIN - 2.5 V) + 6 MHz Note: VDDAPPMIN is the minimum voltage of the PICmicro(R) device in the application. DS30475A-page 312 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 25.1 DC Characteristics Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions PIC18LCXX8 (Industrial) PIC18CXX8 (Industrial, Extended) Param Symbol Characteristic/ No. Device D001 VDD Supply Voltage PIC18LCXX8 2.5 -- 5.5 V HS, XT, RC and LP osc mode D001 PIC18CXX8 4.2 -- 5.5 V D002 VDR RAM Data Retention Voltage(1) 1.5 -- -- V D003 VPOR VDD Start Voltage to ensure inter-- -- 0.7 V See section on Power-on Reset for nal Power-on Reset signal details VDD Rise Rate to ensure internal 0.05 -- -- V/ms See section on Power-on Reset for D004 SVDD Power-on Reset signal details Brown-out Reset Voltage D005 VBOR PIC18LCXX8 BORV1:BORV0 = 11 2.5 -- 2.66 V BORV1:BORV0 = 10 2.7 -- 2.86 V BORV1:BORV0 = 01 4.2 -- 4.46 V BORV1:BORV0 = 00 4.5 -- 4.78 V -- N.A. D005 PIC18CXX8 BORV1:BORV0 = 1x N.A. V Not in operating voltage range of device -- 4.46 BORV1:BORV0 = 01 4.2 V -- 4.78 BORV1:BORV0 = 00 4.5 V Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD or VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 313 PIC18CXX8 25.1 DC Characteristics (cont'd) Standard Operating Conditions (unless otherwise stated) Operating temperature-40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions PIC18LCXX8 (Industrial) PIC18CXX8 (Industrial, Extended) Param Symbol Characteristic/ No. Device Supply Current(2,4) D010 IDD PIC18LCXX8 D010 D010A D010A D010C D010C D013 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 -- -- -- D013 PIC18CXX8 -- -- D014 PIC18LCXX8 -- -- D014 PIC18CXX8 -- -- 48 TBD A A -- -- -- -- -- TBD 50 50 50 50 mA mA mA mA mA -- -- -- -- -- -- -- -- -- -- TBD 48 TBD 45 45 mA A A mA mA -- -- 4 mA Legend: Note 1: 2: 3: 4: -- -- TBD A -- -- TBD A Rows are shaded for improved readability. This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. XT, RC, RCIO osc configurations FOSC = 4 MHz, VDD = 2.5V XT, RC, RCIO osc configurations FOSC = 4 MHz, VDD = 4.2V LP osc configuration FOSC = 32 kHz, VDD = 2.5V LP osc configuration FOSC = 32 kHz, VDD = 4.2V EC, ECIO osc configurations, Fosc = 40 MHz, VDD = 5.5V EC, ECIO osc configurations, Fosc = 40 MHz, VDD = 5.5V HS osc configurations Fosc = 6 MHz, VDD = 2.5V Fosc = 25 MHz, VDD = 5.5V HS + PLL osc configuration Fosc = 10 MHz, VDD = 5.5V HS osc configurations Fosc = 25 MHz, VDD = 5.5V HS + PLL osc configuration Fosc = 10 MHz, VDD = 5.5V Timer1 osc configuration FOSC = 32 kHz, VDD = 2.5V FOSC = 32 kHz, VDD = 2.5V, 25C OSCB osc configuration FOSC = 32 kHz, VDD = 4.2V FOSC = 32 kHz, VDD = 4.2V, 25C DS30475A-page 314 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 25.1 DC Characteristics (cont'd) Standard Operating Conditions (unless otherwise stated) Operating temperature-40C TA +85C for industrial Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Typ Max Units Conditions PIC18LCXX8 (Industrial) PIC18CXX8 (Industrial, Extended) Param Symbol Characteristic/ No. Device D020 IPD Power-down Current(3) PIC18LCXX8 -- <2.5 5 A VDD = 2.5V, -40C to +85C -- -- 36 A VDD = 5.5V, -40C to +85C -- -- TBD A VDD = 2.5V, 25C D020 PIC18CXX8 -- <1 TBD A VDD = 4.2V, -40C to +85C -- -- 36 A VDD = 5.5V, -40C to +85C D020A -- -- TBD A VDD = 4.2V, 25C D021B -- TBD TBD A VDD = 4.2V, -40C to +125C -- -- 42 VDD = 5.5V, -40C to +125C Module Differential Current D022 IWDT PIC18LCXX8 -- -- 12 A VDD = 2.5V Watchdog Timer -- -- 25 A VDD = 5.5V -- -- TBD A VDD = 2.5V, 25C D022 PIC18CXX8 -- -- 25 A VDD = 5.5V, -40C to +85C Watchdog Timer -- -- TBD A VDD = 5.5V, -40C to +125C -- -- TBD A VDD = 4.2V, 25C D022A IBOR PIC18LCXX8 -- -- 50 A VDD = 5.5V Brown-out Reset -- -- TBD A VDD = 2.5V, 25C D022A PIC18CXX8 -- -- 50 A VDD = 5.5V, -40C to +85C Brown-out Reset -- -- TBD A VDD = 5.5V, -40C to +125 -- -- TBD A VDD = 4.2V, 25C PIC18LCXX8 -- -- 50 A VDD = 2.5V D022B ILVD Low Voltage Detect -- -- TBD A VDD = 2.5V, 25C D022B PIC18CXX8 -- -- TBD A VDD = 4.2V, -40C to +85C Low Voltage Detect -- -- TBD A VDD = 4.2V, -40C to +125C -- -- TBD A VDD = 4.2V, 25C D025 IOSCB PIC18LCXX8 -- -- 3 A VDD = 2.5V Timer1 Oscillator -- -- TBD A VDD = 2.5V, 25C D025 PIC18CXX8 -- -- TBD A VDD = 4.2V, -40C to +85C Timer1 Oscillator -- -- TBD A VDD = 4.2V, -40C to +125C -- -- TBD A VDD = 4.2V, 25C Legend: Rows are shaded for improved readability. Note 1: This is the limit to which VDD can be lowered in SLEEP mode or during a device RESET without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tri-stated, pulled to VDD MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS, and all features that add delta current disabled (such as WDT, Timer1 Oscillator, BOR, ...). 4: For RC osc configuration, current through REXT is not included. The current through the resistor can be estimated by the formula Ir = VDD/2REXT (mA) with REXT in kOhm. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 315 PIC18CXX8 25.2 DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Max Units Conditions DC CHARACTERISTICS Param Symbol Characteristic/ No. Device Input Low Voltage VIL I/O ports: D030 with TTL buffer D030A D031 with Schmitt Trigger buffer RC3 and RC4 D032 MCLR D032A OSC1 (in XT, HS and LP modes) and T1OSI D033 OSC1(in RC mode)(1) VIH Input High Voltage I/O ports: D040 with TTL buffer D040A D041 D042 D042A D043 VHYS D050 IIL D060 D061 D063 VSS -- VSS VSS VSS VSS VSS 0.15VDD 0.8 0.2VDD 0.3VDD 0.2VDD 0.3VDD 0.2VDD V V V V V V V VDD < 4.5V 4.5V VDD 5.5V with Schmitt Trigger buffer RC3 and RC4 MCLR OSC1 (in XT, HS and LP modes) and T1OSI 0.9VDD OSC1 (RC mode)(1) Hysteresis of Schmitt Trigger Inputs TBD Input Leakage Current(2,3) I/O ports -- 0.25VDD + 0.8V 2.0 0.8VDD 0.7VDD 0.8VDD 0.7VDD VDD VDD VDD VDD VDD VDD VDD TBD 1 V V V V V V V V A VDD < 4.5V 4.5V VDD 5.5V MCLR -- 5 A OSC1 -- 5 A IPU Weak Pull-up Current D070 IPURB PORTB weak pull-up current 50 400 A VDD = 5V, VPIN = VSS Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. VSS VPIN VDD, Pin at hi-impedance Vss VPIN VDD Vss VPIN VDD DS30475A-page 316 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 25.2 DC Characteristics: PIC18CXX8 (Industrial, Extended) and PIC18LCXX8 (Industrial) (cont'd) Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Min Max Units Conditions DC CHARACTERISTICS Param Symbol Characteristic/ No. Device Output Low Voltage VOL D080 I/O ports D080A D083 D083A VOH D090 D090A D092 D092A VOD D150 Open-drain High Voltage OSC2/CLKO (RC mode) Output High Voltage(3) I/O ports OSC2/CLKO (RC mode) -- -- -- -- 0.6 0.6 0.6 0.6 V V V V IOL = 8.5 mA, VDD = 4.5V, -40C to +85C IOL = 7.0 mA, VDD = 4.5V, -40C to +125C IOL = 1.6 mA, VDD = 4.5V, -40C to +85C IOL = 1.2 mA, VDD = 4.5V, -40C to +125C IOH = -3.0 mA, VDD = 4.5V, -40C to +85C IOH = -2.5 mA, VDD = 4.5V, -40C to +125C IOH = -1.3 mA, VDD = 4.5V, -40C to +85C IOH = -1.0 mA, VDD = 4.5V, -40C to +125C VDD - 0.7 VDD - 0.7 VDD - 0.7 VDD - 0.7 -- -- -- -- V V V V -- 7.5 V RA4 pin Capacitive Loading Specs on Output Pins D101 CIO All I/O pins and OSC2 -- 50 pF To meet the AC Timing Specifications (in RC mode) SCL, SDA -- 400 pF In I2C mode D102 CB Note 1: In RC oscillator configuration, the OSC1/CLKI pin is a Schmitt Trigger input. It is not recommended that the PICmicro device be driven with an external clock while in RC mode. 2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 3: Negative current is defined as current sourced by the pin. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 317 PIC18CXX8 FIGURE 25-3: LOW VOLTAGE DETECT CHARACTERISTICS VDD (LVDIF can be cleared in software) VLVD (LVDIF set by hardware) LVDIF TABLE 25-1: LOW VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Param No. D420 Symbol VLVD LVD Voltage Characteristic/ LVDL<3:0> = 0100 LVDL<3:0> = 0101 LVDL<3:0> = 0110 LVDL<3:0> = 0111 LVDL<3:0> = 1000 LVDL<3:0> = 1001 LVDL<3:0> = 1010 LVDL<3:0> = 1011 LVDL<3:0> = 1100 LVDL<3:0> = 1101 LVDL<3:0> = 1110 Min 2.5 2.7 2.8 3.0 3.3 3.5 3.6 3.8 4.0 4.2 4.5 Max 2.66 2.86 2.98 3.2 3.52 3.72 3.84 4.04 4.26 4.46 4.78 Units V V V V V V V V V V V Conditions DS30475A-page 318 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 25-2: EPROM PROGRAMMING REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +40C Characteristic Voltage on MCLR/VPP pin Supply voltage during programming Current into MCLR/VPP pin Supply current during programming Min 12.75 4.75 -- -- 100 Max 13.25 5.25 50 30 1000 Units V V mA mA s Terminated via internal/external interrupt or a RESET hrs hrs (Note 2) Conditions DC CHARACTERISTICS Param. No. D110 D111 D112 D113 D114 D115 Sym VPP VDDP IPP IDDP Internal Program Memory Programming Specs (Note 1) TPROG Programming pulse width TERASE EPROM erase time Device operation 3V Device operation 3V 4 TBD -- -- Note 1: These specifications are for the programming of the on-chip program memory EPROM through the use of the table write instructions. The complete programming specifications can be found in: PIC18CXX8 Programming Specifications (Literature number DS39028). 2: The MCLR/VPP pin may be kept in this range at times other than programming, but is not recommended. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 319 PIC18CXX8 25.3 25.3.1 AC (Timing) Characteristics TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings: pp cc CCP1 ck CLKO cs CS di SDI do SDO dt Data-in io I/O port mc MCLR Uppercase letters and their meanings: S F Fall H High I Invalid (Hi-impedance) L Low I2C only AA output access BUF Bus free TCC:ST (I2C specifications only) CC HD Hold ST DAT DATA input hold STA START condition 3. TCC:ST 4. Ts T (I2C specifications only) (I2C specifications only) Time osc rd rw sc ss t0 t1 wr OSC1 RD RD or WR SCK SS T0CKI T1CKI WR P R V Z High Low Period Rise Valid Hi-impedance High Low SU STO Setup STOP condition DS30475A-page 320 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 25.3.2 TIMING CONDITIONS The temperature and voltages specified in Table 25-3 apply to all timing specifications, unless otherwise noted. Figure 25-4 specifies the load conditions for the timing specifications. TABLE 25-3: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions (unless otherwise stated) Operating temperature -40C TA +85C for industrial -40C TA +125C for extended Operating voltage VDD range as described in DC spec Section 25.1. LC parts operate for industrial temperatures only. AC CHARACTERISTICS FIGURE 25-4: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load condition 1 VDD/2 CL VSS Pin VSS CL RL = 464 CL = 50 pF for all pins except OSC2/CLKO and including D and E outputs as ports Load condition 2 RL Pin 2000 Microchip Technology Inc. Advanced Information DS30475A-page 321 PIC18CXX8 25.3.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 25-5: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 2 3 3 4 4 CLKOUT TABLE 25-4: 1A EXTERNAL CLOCK TIMING REQUIREMENTS Characteristic External CLKIN Frequency(1) Min DC DC 4 DC DC DC 0.1 4 4 5 250 40 100 5 5 250 250 100 40 5 Max 40 40 10 40 40 4 4 25 10 200 -- -- -- -- -- -- 10,000 10,000 100 -- Units MHz MHz MHz kHz MHz MHz MHz MHz MHz kHz ns ns ns s ns ns ns ns ns s Conditions XT osc HS osc HS + PLL osc LP osc EC RC osc XT osc HS osc HS + PLL osc LP osc mode XT and RC osc HS osc HS + PLL osc LP osc EC RC osc XT osc HS osc HS + PLL osc LP osc Param. No. Symbol Fosc Oscillator Frequency(1) 1 Tosc External CLKIN Period(1) Oscillator Period(1) 2 3 100 -- ns TCY = 4/FOSC 30 -- ns XT osc 2.5 -- ns LP osc 10 -- s HS osc 4 TosR, External Clock in (OSC1) -- 20 ns XT osc Rise or Fall Time TosF -- 50 ns LP osc -- 7.5 ns HS osc Note 1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. TCY TosL, TosH Instruction Cycle Time(1) External Clock in (OSC1) High or Low Time DS30475A-page 322 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 25-5: Param Symbol No. 7 TPLL CLK PLL CLOCK TIMING SPECIFICATION (VDD = 4.2V - 5.5V) Characteristic PLL Start-up Time (Lock Time) CLKOUT Stability (Jitter) using PLL Min -- -2 Max 2 +2 Units ms % Conditions 2000 Microchip Technology Inc. Advanced Information DS30475A-page 323 PIC18CXX8 FIGURE 25-6: CLKOUT AND I/O TIMING Q4 OSC1 10 CLKOUT 13 14 I/O Pin (input) 17 I/O Pin (output) old value 15 new value 19 12 18 16 11 Q1 Q2 Q3 20, 21 Note: Refer to Figure 25-4 for load conditions. TABLE 25-6: Param. No. 10 11 12 13 14 15 16 17 18 18A CLKOUT AND I/O TIMING REQUIREMENTS Characteristic Min Typ Max Units Conditions ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (1) (1) (1) (1) (1) (1) (1) Symbol TosH2ckL TosH2ckH TckR TckF TckL2ioV TioV2ckH TckH2ioI TosH2ioV TosH2ioI OSC1 to CLKOUT -- 75 200 OSC1 to CLKOUT -- 75 200 CLKOUT rise time -- 35 100 CLKOUT fall time -- 35 100 CLKOUT to Port out valid -- -- 0.5TCY + 20 Port in valid before CLKOUT 0.25TCY + 25 -- -- Port in hold after CLKOUT 0 -- -- OSC1 (Q1 cycle) to Port out valid -- 50 150 OSC1 (Q2 cycle) to PIC18CXX8 100 -- -- Port input invalid PIC18LCXX8 200 -- -- (I/O in hold time) 19 TioV2osH Port input valid to OSC1 0 -- -- (I/O in setup time) 20 TioR Port output rise time PIC18CXX8 -- 10 25 20A PIC18LCXX8 -- -- 60 21 TioF Port output fall time PIC18CXX8 -- 10 25 21A PIC18LCXX8 -- -- 60 22 TINP INT pin high or low time TCY -- -- 23 TRBP RB7:RB4 change INT high or low time TCY -- -- 24 TRCP RC7:RC4 change INT high or low time 20 -- -- These parameters are asynchronous events, not related to any internal clock edges. Note 1: Measurements are taken in RC mode where CLKO pin output is 4 x TOSC. DS30475A-page 324 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR Internal POR 33 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset 34 I/O Pins Note: Refer to Figure 25-4 for load conditions. 32 30 31 34 FIGURE 25-8: BROWN-OUT RESET TIMING BVDD VDD 35 VBGAP = 1.2V VIRVST Enable Internal Reference Voltage Internal Reference Voltage stable 36 TABLE 25-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Characteristic MCLR Pulse Width (low) Watchdog Timer Time-out Period (No Prescaler) Oscillation Start-up Timer Period Power up Timer Period I/O Hi-impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Time for Internal Reference Voltage to become stable Min 2 7 1024TOSC 28 -- 200 -- Typ -- 18 -- 72 2 -- 20 Max -- 33 1024TOSC 132 -- -- 50 Units s ms -- ms s s s VDD BVDD (See D005) TOSC = OSC1 period Conditions Param. Symbol No. 30 31 32 33 34 35 36 TmcL TWDT TOST TPWRT TIOZ TBOR TIVRST 2000 Microchip Technology Inc. Advanced Information DS30475A-page 325 PIC18CXX8 FIGURE 25-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1OSO/T1CKI 45 46 47 TMR0 or TMR1 Note: Refer to Figure 25-4 for load conditions. 48 TABLE 25-8: Param Symbol No. 40 41 42 Tt0H Tt0L Tt0P TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period No Prescaler With Prescaler No Prescaler With Prescaler No Prescaler With Prescaler Min 0.5TCY + 20 10 0.5TCY + 20 10 TCY + 10 Greater of: 20 nS or TCY + 40 N 0.5TCY + 20 10 25 30 50 0.5TCY + 5 10 25 30 TBD Greater of: 20 nS or TCY + 40 N 60 DC 2Tosc Max -- -- -- -- -- -- Units ns ns ns ns ns ns Conditions N = prescale value (1, 2, 4,..., 256) 45 Tt1H T1CKI High Time 46 Tt1L T1CKI Low Time 47 Tt1P T1CKI Input Period Synchronous, no prescaler Synchronous, PIC18CXX8 with prescaler PIC18LCXX8 Asynchronous PIC18CXX8 PIC18LCXX8 Synchronous, no prescaler Synchronous, PIC18CXX8 with prescaler PIC18LCXX8 Asynchronous PIC18CXX8 PIC18LCXX8 Synchronous -- -- -- -- -- -- -- -- -- TBD -- ns ns ns ns ns ns ns ns ns ns ns N = prescale value (1, 2, 4, 8) 48 Asynchronous Ft1 T1CKI oscillator input frequency range Tcke2tmrI Delay from external T1CKI clock edge to timer increment -- 50 7Tosc ns kHz -- DS30475A-page 326 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-10: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) CCPx (Capture Mode) 50 52 51 CCPx (Compare or PWM Mode) 53 Note: Refer to Figure 25-4 for load conditions. 54 TABLE 25-9: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Characteristic CCPx input low No Prescaler time With PIC18CXX8 Prescaler PIC18LCXX8 No Prescaler With PIC18CXX8 Prescaler PIC18LCXX8 CCPx input period CCPx output fall time CCPx output fall time PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 CCPx input high time Min 0.5TCY + 20 10 20 0.5TCY + 20 10 20 3TCY + 40 N -- -- -- -- Max -- -- -- -- -- -- -- 25 45 25 45 Units ns ns ns ns ns ns ns ns ns ns ns Conditions Param. Symbol No. 50 TccL 51 TccH 52 53 54 TccP TccR TccF N = prescale value (1,4 or 16) 2000 Microchip Technology Inc. Advanced Information DS30475A-page 327 PIC18CXX8 FIGURE 25-11: PARALLEL SLAVE PORT TIMING (PIC18C658 AND PIC18C858) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 63 Note: Refer to Figure 25-4 for load conditions. 64 TABLE 25-10: PARALLEL SLAVE PORT REQUIREMENTS (PIC18C658 AND PIC18C858) Param. No. 62 63 64 65 66 Symbol TdtV2wrH TwrH2dtI TrdL2dtV TrdH2dtI TibfINH Characteristic Data-in valid before WR or CS (setup time) WR or CS to data-in invalid PIC18CXX8 (hold time) PIC18LCXX8 RD and CS to data-out valid RD or CS to data-out invalid Inhibit the IBF flag bit being cleared from WR or CS Min 20 25 20 35 -- -- 10 -- Max -- -- -- -- 80 90 30 3TCY Units ns ns ns ns ns ns ns ns Conditions Extended Temp range Extended Temp range DS30475A-page 328 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-12: EXAMPLE SPI MASTER MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 78 79 SCK (CKP = 1) 79 78 80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 25-4 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1 LSb LSb In TABLE 25-11: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No. 70 71 71A 72 72A 73 73A 74 75 76 78 79 80 TdiV2scH, TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TscR TscF TscH2doV, TscL2doV TscL Symbol TssL2scH, TssL2scL TscH Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- -- PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 -- -- -- -- -- Max Units -- -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) Conditions Setup time of SDI data input to SCK edge Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18CXX8 PIC18LCXX8 SCK output fall time (Master mode) SDO data output valid after SCK edge Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 329 PIC18CXX8 FIGURE 25-13: EXAMPLE SPI MASTER MODE TIMING (CKE = 1) SS 81 SCK (CKP = 0) 71 73 SCK (CKP = 1) 80 78 72 79 SDO MSb 75, 76 Bit6 - - - - - -1 LSb SDI MSb In 74 Bit6 - - - -1 LSb In Note: Refer to Figure 25-4 for load conditions. TABLE 25-12: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. Symbol No. 71 TscH 71A 72 TscL 72A 73 TdiV2scH, TdiV2scL 73A TB2B 74 75 76 78 TscH2diL, TscL2diL TdoR TdoF TscR Characteristic SCK input high time (Slave mode) Continuous Single Byte SCK input low time Continuous (Slave mode) Single Byte Setup time of SDI data input to SCK edge Min 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- -- -- -- -- -- -- TCY Max Units -- -- -- -- -- -- -- 25 45 25 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions (Note 1) (Note 1) Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SCK output rise time (Master mode) PIC18CXX8 PIC18LCXX8 (Note 2) PIC18CXX8 PIC18LCXX8 79 TscF SCK output fall time (Master mode) 80 TscH2doV, SDO data output valid after PIC18CXX8 TscL2doV SCK edge PIC18LCXX8 81 TdoV2scH, SDO data output setup to SCK edge TdoV2scL Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS30475A-page 330 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-14: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 71 72 83 78 79 SCK (CKP = 1) 79 78 80 SDO MSb 75, 76 SDI MSb In 74 73 Note: Refer to Figure 25-4 for load conditions. Bit6 - - - -1 Bit6 - - - - - -1 LSb 77 LSb In TABLE 25-13: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0)) Parm. No. 70 71 71A 72 72A 73 73A 74 75 76 77 78 79 80 83 TscL Symbol Characteristic Min TCY Continuous Single Byte Continuous Single Byte 1.25TCY + 30 40 1.25TCY + 30 40 100 1.5TCY + 40 100 -- -- 10 PIC18CXX8 PIC18LCXX8 -- PIC18CXX8 PIC18LCXX8 1.5TCY + 40 -- -- Max Units Conditions -- -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 2) (Note 1) (Note 1) TssL2scH, SS to SCK or SCK input TssL2scL TscH SCK input high time (Slave mode) SCK input low time (Slave mode) TdiV2scH, Setup time of SDI data input to SCK edge TdiV2scL TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) PIC18CXX8 PIC18LCXX8 TscH2doV, SDO data output valid after SCK TscL2doV edge TscH2ssH, SS after SCK edge TscL2ssH Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 331 PIC18CXX8 FIGURE 25-15: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb 75, 76 Bit6 - - - - - -1 LSb 77 SDI MSb In Bit6 - - - -1 LSb In 74 Note: Refer to Figure 25-4 for load conditions. TABLE 25-14: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Parm. No. 70 71 71A 72 72A 73A 74 75 76 77 78 79 80 82 83 TB2B TscH2diL, TscL2diL TdoR TdoF TssH2doZ TscR TscF TscH2doV, TscL2doV TssL2doV TscH2ssH, TscL2ssH TscL Symbol TssL2scH, TssL2scL TscH Characteristic SS to SCK or SCK input SCK input high time (Slave mode) SCK input low time (Slave mode) Continuous Single Byte Continuous Single Byte Min TCY 1.25TCY + 30 40 1.25TCY + 30 40 1.5TCY + 40 100 -- -- -- 10 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 -- -- -- -- -- -- -- 1.5TCY + 40 Max Units Conditions -- -- -- -- -- -- -- 25 45 25 50 25 45 25 50 100 50 100 -- ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns (Note 1) (Note 2) (Note 1) Last clock edge of Byte1 to the 1st clock edge of Byte2 Hold time of SDI data input to SCK edge SDO data output rise time SDO data output fall time SS to SDO output hi-impedance SCK output rise time (Master mode) SCK output fall time (Master mode) SDO data output valid after SCK edge SDO data output valid after SS edge SS after SCK edge PIC18CXX8 PIC18LCXX8 Note 1: Requires the use of parameter # 73A. 2: Only if parameter #s 71A and 72A are used. DS30475A-page 332 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-16: I2C BUS START/STOP BITS TIMING SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 25-4 for load conditions. STOP Condition TABLE 25-15: I2C BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Parm. No. 90 91 92 93 Symbol TSU:STA Characteristic 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4700 600 4000 600 4700 600 4000 600 Max -- -- -- -- -- -- -- -- Units ns ns ns ns Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated START condition Setup time THD:STA START condition Hold time TSU:STO STOP condition Setup time THD:STO STOP condition Hold time 2000 Microchip Technology Inc. Advanced Information DS30475A-page 333 PIC18CXX8 FIGURE 25-17: I2C BUS DATA TIMING 103 100 101 102 SCL 90 91 106 107 92 SDA In 110 109 109 SDA Out Note: Refer to Figure 25-4 for load conditions. TABLE 25-16: I2C BUS DATA REQUIREMENTS (SLAVE MODE) Param. No. 100 Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode SSP Module 101 TLOW Clock low time 100 kHz mode 400 kHz mode SSP module 102 TR SDA and SCL rise time SDA and SCL fall time START condition setup time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode Min 4.0 0.6 1.5TCY 4.7 1.3 1.5TCY -- 20 + 0.1Cb -- 20 + 0.1Cb 4.7 0.6 4.0 0.6 0 0 250 100 4.7 0.6 -- -- 4.7 1.3 -- Max -- -- -- -- -- -- 1000 300 300 300 -- -- -- -- -- 0.9 -- -- -- -- 3500 -- -- -- 400 Units Conditions PIC18CXX8 must operate at a minimum of 1.5 MHz PIC18CXX8 must operate at a minimum of 10 MHz PIC18CXX8 must operate at a minimum of 1.5 MHz PIC18CXX8 must operate at a minimum of 10 MHz s s s s ns ns ns ns ns Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for repeated START condition After this period the first clock pulse is generated 103 TF 90 91 106 107 92 109 110 TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF s s s s ns START condition hold 100 kHz mode time 400 kHz mode Data input hold time 100 kHz mode 400 kHz mode Data input setup time 100 kHz mode 400 kHz mode STOP condition setup time Output valid from clock Bus free time 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode 100 kHz mode 400 kHz mode s ns ns (Note 2) s s ns ns (Note 1) Time the bus must be free before a new transmission can start s s pF D102 Note 1: 2: Cb Bus capacitive loading As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tsu;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, TR max. + tsu;DAT = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification). DS30475A-page 334 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-18: MASTER SSP I2C BUS START/STOP BITS TIMING WAVEFORMS SCL 90 SDA 91 92 93 START Condition Note: Refer to Figure 25-4 for load conditions. STOP Condition TABLE 25-17: MASTER SSP I2C BUS START/STOP BITS REQUIREMENTS Param. Symbol No. 90 TSU:STA Characteristic START condition Setup time 91 THD:STA START condition Hold time 92 TSU:STO STOP condition Setup time 93 THD:STO STOP condition Hold time Min Max -- -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns Units Conditions Only relevant for Repeated START condition After this period, the first clock pulse is generated 100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode (1) 2(TOSC)(BRG + 1) 100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1) 100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode(1) 2(TOSC)(BRG + 1) 100 kHz mode 2(TOSC)(BRG + 1) 400 kHz mode 2(TOSC)(BRG + 1) 1 MHz mode (1) 2(TOSC)(BRG + 1) Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 335 PIC18CXX8 FIGURE 25-19: MASTER SSP I2C BUS DATA TIMING 103 100 101 102 SCL SDA In 90 91 106 107 92 109 109 110 SDA Out Note: Refer to Figure 25-4 for load conditions. TABLE 25-18: MASTER SSP I2C BUS DATA REQUIREMENTS Param. Symbol No. THIGH 100 Characteristic Clock high time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode Min 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- 20 + 0.1Cb -- -- 20 + 0.1Cb -- 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 0 0 TBD 250 100 TBD 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) 2(TOSC)(BRG + 1) -- -- -- 4.7 1.3 TBD -- Max -- -- -- -- -- -- 1000 300 300 300 300 100 -- -- -- -- -- -- -- 0.9 -- -- -- -- -- -- -- 3500 1000 -- -- -- -- 400 Units ms ms ms ms ms ms ns ns ns ns ns ns ms ms ms ms ms ms ns ms ns ns ns ns ms ms ms ns ns ns ms ms ms pF Time the bus must be free before a new transmission can start (Note 2) Cb is specified to be from 10 to 400 pF Cb is specified to be from 10 to 400 pF Only relevant for Repeated START condition After this period the first clock pulse is generated Conditions 101 TLOW Clock low time 102 TR SDA and SCL rise time SDA and SCL fall time 103 TF 90 TSU:STA 1 MHz mode(1) START condition 100 kHz mode setup time 400 kHz mode 1 MHz mode(1) START condition 100 kHz mode hold time 400 kHz mode Data input hold time Data input setup time STOP condition setup time 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 91 THD:STA 106 THD:DAT 107 TSU:DAT 92 TSU:STO 109 TAA 1 MHz mode(1) Output valid from 100 kHz mode clock 400 kHz mode Bus free time 1 MHz mode(1) 100 kHz mode 400 kHz mode 110 TBUF D102 Cb 1 MHz mode(1) Bus capacitive loading Note 1: Maximum pin capacitance = 10 pF for all I2C pins. 2: A fast mode I2C bus device can be used in a standard mode I2C bus system, but parameter #107 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line. Before the SCL line is released, parameter #102+ parameter #107 = 1000 + 250 = 1250 ns (for 100 kHz mode). DS30475A-page 336 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 FIGURE 25-20: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 120 121 121 122 Note: Refer to Figure 25-4 for load conditions. TABLE 25-19: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No. 120 Symbol Characteristic Min Max Units Conditions TckH2dtV SYNC XMIT (Master & Slave) Clock high to data-out valid Tckrf Tdtrf Clock out rise time and fall time (Master mode) Data-out rise time and fall time 121 122 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 -- -- -- -- -- -- 40 100 20 50 20 50 ns ns ns ns ns ns 2000 Microchip Technology Inc. Advanced Information DS30475A-page 337 PIC18CXX8 FIGURE 25-21: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING RC6/TX/CK pin RC7/RX/DT pin 125 126 Note: Refer to Figure 25-4 for load conditions. TABLE 25-20: USART SYNCHRONOUS RECEIVE REQUIREMENTS Param. No. 125 126 Symbol TdtV2ckl TckL2dtl Characteristic SYNC RCV (Master & Slave) Data-hold before CK (DT hold time) Data-hold after CK (DT hold time) Min Max Units Conditions 10 15 -- -- ns ns DS30475A-page 338 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 TABLE 25-21: A/D CONVERTER CHARACTERISTICS: Param Symbol No. A01 A03 A04 A05 A06 A10 A20 A20A A21 A22 A25 A30 A40 VREFH VREFL VAIN ZAIN IAD NR EIL EDL EFS EOFF -- VREF PIC18CXX8 (INDUSTRIAL, EXTENDED) PIC18LCXX8 (INDUSTRIAL) Typ -- -- -- -- -- -- -- -- -- -- Max 10 TBD <1 TBD <1 TBD <1 TBD <1 TBD -- -- AVDD + 0.3V AVDD VREF + 0.3V 10.0 -- -- 1000 Units bit bit Conditions VREF = VDD 3.0V VREF = VDD < 3.0V Characteristic Resolution Integral linearity error Differential linearity error Full scale error Offset error Monotonicity Reference voltage (VREFH - VREFL) Reference voltage High Reference voltage Low Analog input voltage Recommended impedance of analog voltage source A/D conversion current (VDD) PIC18CXX8 PIC18LCXXX Min -- -- -- -- -- -- -- -- -- -- 0V 3V AVSS AVSS - 0.3V AVSS - 0.3V -- -- -- 10 LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V LSb VREF = VDD 3.0V LSb VREF = VDD < 3.0V -- V V V V V k A A A Average current consumption when A/D is on(1). During VAIN acquisition. Based on differential of VHOLD to VAIN. To charge CHOLD see Section 18.0. During A/D conversion cycle. For 10-bit resolution VSS VAIN VREF guaranteed(3) -- -- -- -- -- -- 180 90 -- A50 IREF VREF input current(2) -- -- 10 A Note 1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. VREF current is from RA2/AN2/VREF- and RA3/AN3/VREF+ pins or AVDD and AVSS pins, whichever is selected as reference input. 2: VSS VAIN VREF 3: The A/D conversion result either increases or remains constant as the analog input increases. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 339 PIC18CXX8 FIGURE 25-22: A/D CONVERSION TIMING BSF ADCON0, GO Note 2 Q4 130 A/D CLK 132 131 A/D DATA 9 8 7 ... ... 2 1 0 ADRES OLD_DATA NEW_DATA ADIF GO SAMPLING STOPPED DONE TCY SAMPLE Note 1: 2: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts.This allows the SLEEP instruction to be executed. This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input. TABLE 25-22: A/D CONVERSION REQUIREMENTS Param No. 130 Symbol TAD Characteristic A/D clock period PIC18CXX8 PIC18LCXX8 PIC18CXX8 PIC18LCXX8 131 132 135 136 TCNV TACQ TSWC TAMP Conversion time (not including acquisition time)(1) Acquisition time(3) Switching time from convert sample Amplifier settling time (Note 2) Min 1.6 3.0 2.0 3.0 11 15 10 -- 1 Max 20(5) 20 (5) Units s s s s TAD s s s Conditions TOSC based, VREF 3.0V TOSC based, VREF full range A/D RC mode A/D RC mode 6.0 9.0 12 -- -- (Note 4) -- -40C Temp 125C 0C Temp 125C This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 5 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). Note 1: ADRES register may be read on the following TCY cycle. 2: See Section 18.0 for minimum conditions, when input voltage has changed more than 1 LSb. 3: The time for the holding capacitor to acquire the "New" input voltage, when the voltage changes full scale after the conversion (AVDD to AVSS, or AVSS to AVDD). The source impedance (RS) on the input channels is 50 . 4: On the next Q4 cycle of the device clock. 5: The time of the A/D clock period is dependent on the device frequency and the TAD clock divider. DS30475A-page 340 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 26.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables are not available at this time. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 341 PIC18CXX8 NOTES: DS30475A-page 342 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 27.0 27.1 PACKAGING INFORMATION Package Marking Information 64-Lead TQFP Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18C658-I/PT 0017017 68-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC18C658-I/L 0017017 80-Lead TQFP Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC18C858-I/PT 0017017 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code and traceability code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 343 PIC18CXX8 Package Marking Information (Cont'd) 84-Lead PLCC Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC18C858-I/L 0017017 DS30475A-page 344 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 64-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D 2 1 B n CH x 45 A c L A1 (F) A2 Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH MIN .039 .037 .002 .018 0 .463 .463 .390 .390 .005 .007 .025 5 5 INCHES NOM 64 .020 16 .043 .039 .006 .024 .039 3.5 .472 .472 .394 .394 .007 .009 .035 10 10 MAX MIN .047 .041 .010 .030 7 .482 .482 .398 .398 .009 .011 .045 15 15 MILLIMETERS* NOM 64 0.50 16 1.00 1.10 0.95 1.00 0.05 0.15 0.45 0.60 1.00 0 3.5 11.75 12.00 11.75 12.00 9.90 10.00 9.90 10.00 0.13 0.18 0.17 0.22 0.64 0.89 5 10 5 10 MAX 1.20 1.05 0.25 0.75 7 12.25 12.25 10.10 10.10 0.23 0.27 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-085 2000 Microchip Technology Inc. Advanced Information DS30475A-page 345 PIC18CXX8 68-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC) E E1 #leads=n1 D1 D CH2 x 45 n 12 CH1 x 45 A2 A A3 32 c B1 E2 Units Dimension Limits n p INCHES* NOM 68 .050 17 .173 .153 .028 .029 .045 .005 .990 .990 .954 .954 .920 .920 .011 .029 .020 5 5 B D2 p A1 MIN MAX MIN Number of Pins Pitch Pins per Side n1 Overall Height A .165 .180 .145 .160 Molded Package Thickness A2 .035 Standoff A1 .020 Side 1 Chamfer Height A3 .024 .034 Corner Chamfer 1 CH1 .040 .050 Corner Chamfer (others) CH2 .000 .010 Overall Width E .985 .995 Overall Length D .985 .995 Molded Package Width E1 .950 .958 Molded Package Length D1 .950 .958 Footprint Width E2 .890 .930 Footprint Length D2 .890 .930 c Lead Thickness .008 .013 Upper Lead Width B1 .026 .032 Lower Lead Width B .013 .021 0 10 Mold Draft Angle Top Mold Draft Angle Bottom 0 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-049 MILLIMETERS NOM 68 1.27 17 4.19 4.39 3.68 3.87 0.71 0.51 0.61 0.74 1.02 1.14 0.00 0.13 25.02 25.15 25.02 25.15 24.13 24.23 24.13 24.23 22.61 23.37 22.61 23.37 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MAX 4.57 4.06 0.89 0.86 1.27 0.25 25.27 25.27 24.33 24.33 23.62 23.62 0.33 0.81 0.53 10 10 DS30475A-page 346 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 80-Lead Plastic Thin Quad Flatpack (PT) 12x12x1 mm Body, 1.0/0.10 mm Lead Form (TQFP) E E1 #leads=n1 p D1 D B 2 1 n CH x 45 A c L A1 (F) Units Dimension Limits n p n1 A A2 A1 L (F) E D E1 D1 c B CH INCHES NOM 80 .020 20 .043 .039 .004 .024 .039 3.5 .551 .551 .472 .472 .006 .009 .035 10 10 MILLIMETERS* NOM 80 0.50 20 1.00 1.10 0.95 1.00 0.05 0.10 0.45 0.60 1.00 0 3.5 13.75 14.00 13.75 14.00 11.75 12.00 11.75 12.00 0.09 0.15 0.17 0.22 0.64 0.89 5 10 5 10 A2 MIN MAX MIN MAX Number of Pins Pitch Pins per Side Overall Height Molded Package Thickness Standoff Foot Length Footprint (Reference) Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Pin 1 Corner Chamfer Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic .039 .037 .002 .018 0 .541 .541 .463 .463 .004 .007 .025 5 5 .047 .041 .006 .030 7 .561 .561 .482 .482 .008 .011 .045 15 15 1.20 1.05 0.15 0.75 7 14.25 14.25 12.25 12.25 0.20 0.27 1.14 15 15 Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092 2000 Microchip Technology Inc. Advanced Information DS30475A-page 347 PIC18CXX8 84-Lead Plastic Leaded Chip Carrier (L) - Square (PLCC) E E1 #leads=n1 D1 D n 12 CH2 x 45 CH1 x 45 A2 A A3 32 c B1 E2 Units Dimension Limits n p INCHES* NOM 68 .050 17 .165 .173 .145 .153 .028 .020 .024 .029 .040 .045 .000 .005 .985 .990 .985 .990 .950 .954 .950 .954 .890 .920 .890 .920 .008 .011 .026 .029 .013 .020 0 5 0 5 B D2 p A1 MIN MAX MIN Number of Pins Pitch Pins per Side n1 Overall Height A .180 .160 Molded Package Thickness A2 .035 Standoff A1 Side 1 Chamfer Height A3 .034 Corner Chamfer 1 CH1 .050 Corner Chamfer (others) CH2 .010 Overall Width E .995 Overall Length D .995 Molded Package Width E1 .958 Molded Package Length D1 .958 Footprint Width E2 .930 Footprint Length D2 .930 c Lead Thickness .013 Upper Lead Width B1 .032 Lower Lead Width B .021 Mold Draft Angle Top 10 Mold Draft Angle Bottom 10 * Controlling Parameter Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-047 Drawing No. C04-093 MILLIMETERS NOM 68 1.27 17 4.19 4.39 3.68 3.87 0.71 0.51 0.61 0.74 1.02 1.14 0.00 0.13 25.02 25.15 25.02 25.15 24.13 24.23 24.13 24.23 22.61 23.37 22.61 23.37 0.20 0.27 0.66 0.74 0.33 0.51 0 5 0 5 MAX 4.57 4.06 0.89 0.86 1.27 0.25 25.27 25.27 24.33 24.33 23.62 23.62 0.33 0.81 0.53 10 10 DS30475A-page 348 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 APPENDIX A: Revision A This is a new data sheet. DATA SHEET REVISION HISTORY APPENDIX B: DEVICE DIFFERENCES The differences between the PIC18CXX8 devices listed in this data sheet are shown in Table B-1. TABLE B-1: Feature DEVICE DIFFERENCES PIC18C658 32K 1.5K 12 Yes 64-pin 68-pin 68-pin PIC18C858 32K 1.5K 16 Yes No 80-pin 84-pin 84-pin Program Memory (Bytes) Data Memory (Bytes) A/D Channels Parallel Slave Port (PSP) Package Types TQFP PLCC JCERPACK External Memory Capability No 2000 Microchip Technology Inc. Advanced Information DS30475A-page 349 PIC18CXX8 APPENDIX C: DEVICE MIGRATIONS APPENDIX D: This section is intended to describe the functional and electrical specification differences when migrating between functionally similar devices (such as from a PIC16C74A to a PIC16C74B). Not Applicable MIGRATING FROM OTHER PICMICRO DEVICES This discusses some of the issues in migrating from other PICmicro devices to the PIC18CXXX family of devices. D.1 PIC16CXXX to PIC18CXXX See application note AN716. D.2 PIC17CXXX to PIC18CXXX See application note AN726. DS30475A-page 350 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 APPENDIX E: DEVELOPMENT TOOL VERSION REQUIREMENTS This lists the minimum requirements (software/firmware) of the specified development tool to support the devices listed in this data sheet. MPLAB-IDE: MPLAB-SIM: MPLAB-ICE 2000: PIC18CXX8 Processor Module: Part Number PCM 18XB0 PIC18CXX8 Device Adapter: Socket Part Number 64-pin TQFP DVD18P2640 68-pin PLCC DVD18XL680 80-pin TQFP DVD18PQ800 84-pin PLCC DVD18XL840 MPLAB-ICD: PROMATE II: PICSTART Plus: MPASM: MPLAB-C18: CAN-TOOL: Not Available version 5.20 version 2.20 version 2.50 version 1.00 Not available at time of printing. version 5.11 version 7.10 Note: Please read all associated README.TXT files that are supplied with the development tools. These "read me" files will discuss product support and any known limitations. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 351 PIC18CXX8 NOTES: DS30475A-page 352 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 INDEX A A/D ................................................................................... 227 A/D Converter Flag (ADIF Bit) ................................. 230 A/D Converter Interrupt, Configuring ....................... 231 ADCON0 Register ............................................ 227, 229 ADCON1 Register ............................................ 227, 228 ADCON2 Register .................................................... 227 ADRES Register .............................................. 227, 230 Analog Port Pins, Configuring .................................. 233 Block Diagram .......................................................... 230 Block Diagram, Analog Input Model ......................... 231 Configuring the Module ............................................ 231 Conversion Clock (TAD) ........................................... 233 Conversion Status (GO/DONE Bit) .......................... 230 Conversions ............................................................. 234 Converter Characteristics ........................................ 339 converter characteristics .......................................... 318 Effects of a RESET .................................................. 250 Equations ................................................................. 232 Operation During SLEEP ......................................... 250 Sampling Requirements ........................................... 232 Sampling Time ......................................................... 232 Special Event Trigger (CCP) ............................ 130, 234 Timing Diagram ........................................................ 340 Absolute Maximum Ratings ............................................. 311 Acknowledge Error ........................................................... 223 ADCON0 Register .................................................... 227, 229 GO/DONE Bit ........................................................... 230 ADCON1 Register .................................................... 227, 228 ADCON2 Register ............................................................ 227 ADDLW ............................................................................ 267 ADDWF ............................................................................ 267 ADDWFC ......................................................................... 268 ADRES Register ...................................................... 227, 230 AKS .................................................................................. 156 Analog-to-Digital Converter. See A/D ANDLW ............................................................................ 268 ANDWF ............................................................................ 269 Assembler MPASM Assembler .................................................. 305 BSF .......................... 269, 270, 271, 272, 273, 275, 276, 291 BTFSC ............................................................................. 274 BTFSS ............................................................................. 274 BTG ................................................................................. 275 Bus Activity Wake-up Interrupt ........................................ 225 Bus Collision During a RESTART Condition ................... 165 Bus Collision During a START Condition ........................ 163 Bus Collision During a STOP Condition .......................... 166 Bus Off ............................................................................. 226 C CALL ................................................................................ 276 CAN Buffers and Protocol Engine Block Diagram ........... 184 Capture (CCP Module) .................................................... 128 Block Diagram ......................................................... 129 CCP Pin Configuration ............................................ 128 CCPR1H:CCPR1L Registers .................................. 128 Changing Between Capture Prescalers .................. 129 Software Interrupt .................................................... 129 Timer1 Mode Selection ............................................ 128 Capture/Compare/PWM (CCP) ....................................... 127 Capture Mode. See Capture CCP1 ....................................................................... 128 CCPR1H Register ........................................... 128 CCPR1L Register ............................................ 128 CCP2 ....................................................................... 128 CCPR2H Register ........................................... 128 CCPR2L Register ............................................ 128 Compare Mode. See Compare Interaction of Two CCP Modules ............................. 128 PWM Mode. See PWM Timer Resources ..................................................... 128 Timing Diagram ....................................................... 327 Clocking Scheme ............................................................... 45 CLRF ....................................................................... 277, 295 CLRWDT ......................................................................... 277 Code Examples Loading the SSPBUF Register ................................ 142 Code Protection ....................................................... 251, 259 COMF .............................................................................. 278 Comparator Interrupts ...................................................... 241 Comparator Operation ..................................................... 239 Comparator Reference .................................................... 239 Compare (CCP Module) .................................................. 130 Block Diagram ......................................................... 130 CCP Pin Configuration ............................................ 130 CCPR1H:CCPR1L Registers .................................. 130 Software Interrupt .................................................... 130 Special Event Trigger ...................... 119, 125, 130, 234 Timer1 Mode Selection ............................................ 130 Configuration Bits ............................................................ 251 Configuration Mode ......................................................... 210 Configuring the Voltage Reference .................................. 243 CPFSEQ .......................................................................... 278 CPFSGT .......................................................................... 279 CPFSLT ........................................................................... 279 CRC Error ........................................................................ 223 CVRCON Register ........................................................... 243 B Baud Rate Generator ....................................................... 153 BCF .................................................................................. 270 BF .................................................................................... 156 Bit Error ............................................................................ 223 Bit Timing ......................................................................... 218 Bit Timing Configuration Registers .................................. 222 Block Diagrams Baud Rate Generator ............................................... 153 Comparator I/O Operating Modes ............................ 238 PORTK ..................................................................... 108 SSP (SPI Mode) ....................................................... 141 Timer3 ...................................................................... 124 BOR. See Brown-out Reset BRG ................................................................................. 153 Brown-out Reset (BOR) ............................................. 30, 251 Timing Diagram ........................................................ 325 2000 Microchip Technology Inc. Advanced Information DS30475A-page 353 PIC18CXX8 D Data Memory ...................................................................... 48 General Purpose Registers ........................................ 48 Special Function Registers ........................................ 48 DAW ................................................................................. 280 DC Characteristics ........................... 313, 314, 315, 316, 317 DECF ............................................................................... 280 DECFSNZ ........................................................................ 281 DECFSZ ........................................................................... 281 Device Differences ........................................................... 349 Device Functionality ......................................................... 184 Direct Addressing ............................................................... 62 Bus Collision timing ................................................. 162 Clock Arbitration ...................................................... 161 Clock Arbitration Timing (Master Transmit) ............. 161 General Call Address Support ................................. 150 Master Mode 7-bit Reception timing ........................ 158 Master Mode Operation ........................................... 152 Master Mode Start Condition ................................... 154 Master Mode Transmission ..................................... 156 Master Mode Transmit Sequence ............................ 152 Multi-Master Mode ................................................... 162 Repeat START Condition timing .............................. 155 STOP Condition Receive or Transmit timing ........... 160 STOP Condition timing ............................................ 159 Waveforms for 7-bit Reception ................................ 149 Waveforms for 7-bit Transmission ........................... 149 ID Locations ............................................................. 251, 259 INCF ................................................................................ 282 INCFSNZ ......................................................................... 283 INCFSZ ............................................................................ 283 In-Circuit Serial Programming (ICSP) ...................... 251, 259 Indirect Addressing ............................................................ 62 FSR Register ............................................................. 61 Information Processing Time ........................................... 219 Initiating Message Transmission ..................................... 211 Instruction Cycle ................................................................ 45 Instruction Flow/Pipelining ................................................. 46 Instruction Format ............................................................ 263 Instruction Set .................................................................. 261 ADDLW .................................................................... 267 ADDWF .................................................................... 267 ADDWFC ................................................................. 268 ANDLW .................................................................... 268 ANDWF .................................................................... 269 BCF ......................................................................... 270 BSF .................. 269, 270, 271, 272, 273, 275, 276, 291 BTFSC ..................................................................... 274 BTFSS ..................................................................... 274 BTG ......................................................................... 275 CALL ........................................................................ 276 CLRF ............................................................... 277, 295 CLRWDT ................................................................. 277 COMF ...................................................................... 278 CPFSEQ .................................................................. 278 CPFSGT .................................................................. 279 CPFSLT ................................................................... 279 DAW ........................................................................ 280 DECF ....................................................................... 280 DECFSNZ ................................................................ 281 DECFSZ .................................................................. 281 GOTO ...................................................................... 282 INCF ........................................................................ 282 INCFSNZ ................................................................. 283 INCFSZ .................................................................... 283 IORLW ..................................................................... 284 IORWF ..................................................................... 284 MOVFP .................................................................... 286 MOVLB .................................................................... 285 MOVLR ............................................................ 285, 286 MOVLW ................................................................... 287 MOVWF ................................................................... 287 MULLW .................................................................... 288 MULWF .................................................................... 288 NEGW ..................................................................... 289 NOP ......................................................................... 289 RETFIE ............................................................ 291, 292 RETLW .................................................................... 292 E Electrical Characteristics .................................................. 311 Errata ................................................................................... 7 Error Detection ................................................................. 223 Error Interrupt ................................................................... 226 Error Modes ..................................................................... 224 Error Modes and Error Counters ...................................... 223 Error States ...................................................................... 223 F Filter/Mask Truth Table .................................................... 216 Firmware Instructions ....................................................... 261 Form Error ........................................................................ 223 G General Call Address Sequence ...................................... 150 General Call Address Support ......................................... 150 GOTO ............................................................................... 282 H Hard Synchronization ....................................................... 220 I I/O Ports ............................................................................. 89 I2C (SSP Module) ............................................................. 147 ACK Pulse ................................................ 147, 148, 149 Addressing ............................................................... 148 Block Diagram .......................................................... 147 Read/Write Bit Information (R/W Bit) ............... 148, 149 Reception ................................................................. 149 Serial Clock (RC3/SCK/SCL) ................................... 149 Slave Mode .............................................................. 147 Timing Diagram, Data .............................................. 334 Timing Diagram, Start/Stop Bits ............................... 333 Transmission ............................................................ 149 I2C Master Mode Reception ............................................. 156 I2C Master Mode Restart Condition ................................. 155 I2C Module Acknowledge Sequence timing ................................ 159 Baud Rate Generator ............................................... 153 BRG Block Diagram ................................................. 153 BRG Reset due to SDA Collision ............................. 164 BRG Timing ............................................................. 153 Bus Collision Acknowledge .................................................... 162 Restart Condition ............................................. 165 Restart Condition Timing (Case1) .................... 165 Restart Condition Timing (Case2) .................... 165 START Condition ............................................. 163 Start Condition Timing ............................. 163, 164 STOP Condition ............................................... 166 STOP Condition Timing (Case1) ..................... 166 STOP Condition Timing (Case2) ..................... 166 Transmit Timing ............................................... 162 DS30475A-page 354 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 RETURN .................................................................. 293 RLCF ........................................................................ 293 RLNCF ..................................................................... 294 RRCF ....................................................................... 294 RRNCF .................................................................... 295 SLEEP ..................................................................... 296 SUBLW .................................................................... 297 SUBWF ............................................................ 297, 298 SUBWFB .................................................................. 299 SWAPF .................................................................... 300 TABLRD ................................................................... 301 TABLWT .................................................................. 302 TSTFSZ ................................................................... 303 XORLW .................................................................... 303 XORWF .................................................................... 304 Summary Table ........................................................ 264 INT Interrupt (RB0/INT). See Interrupt Sources INTCON Register RBIF Bit ...................................................................... 91 Inter-Integrated Circuit. See I2C Interrupt Acknowledge ..................................................... 226 Interrupt Sources ....................................................... 75, 251 A/D Conversion Complete ....................................... 231 Capture Complete (CCP) ......................................... 129 Compare Complete (CCP) ....................................... 130 Interrupt-on-Change (RB7:RB4 ) ............................... 91 RB0/INT Pin, External ................................................ 88 SSP Receive/Transmit Complete ............................ 135 TMR0 Overflow ........................................................ 116 TMR1 Overflow ................................................ 117, 119 TMR2 to PR2 Match ................................................ 122 TMR2 to PR2 Match (PWM) ............................ 121, 132 TMR3 Overflow ................................................ 123, 125 USART Receive/Transmit Complete ....................... 167 Interrupts .......................................................................... 225 Interrupts, Enable Bits CCP1 Enable (CCP1IE Bit) ...................................... 129 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ................................. 230 CCP1 Flag (CCP1IF Bit) .......................... 128, 129, 130 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ........ 91 IORLW ............................................................................. 284 IORWF ............................................................................. 284 MPLAB Integrated Development Environment Software ..................................................... 305 MULLW ............................................................................ 288 Multi-Master Mode ........................................................... 162 Multiply Examples 16 x 16 Routine ......................................................... 72 16 x 16 Signed Routine ............................................. 73 8 x 8 Routine ............................................................. 72 8 x 8 Signed Routine ................................................. 72 MULWF ............................................................................ 288 N NEGW ............................................................................. 289 NOP ................................................................................. 289 Normal Mode ................................................................... 210 O OPTION_REG Register ..................................................... 64 PS2:PS0 Bits ........................................................... 115 PSA Bit .................................................................... 115 T0CS Bit .................................................................. 115 T0SE Bit .................................................................. 115 OSCCON ........................................................................... 25 OSCCON Register ............................................................. 25 Oscillator Configuration ............................................. 21, 251 HS .............................................................................. 21 HS + PLL ................................................................... 21 LP .............................................................................. 21 RC ....................................................................... 21, 23 RCIO .......................................................................... 21 XT .............................................................................. 21 Oscillator Tolerance ......................................................... 222 Oscillator, Timer1 ............................................. 117, 119, 123 Oscillator, Timer3 ............................................................. 125 Oscillator, WDT ................................................................ 255 Overview .......................................................................... 183 P Packaging ........................................................................ 343 Parallel Slave Port (PSP) ........................................... 95, 109 Block Diagram ......................................................... 109 RE0/RD ................................................................... 109 RE1/WR ................................................................... 109 RE2/CS .................................................................... 109 Read Waveforms ..................................................... 111 Select (PSPMODE Bit) ...................................... 95, 109 Timing Diagram ....................................................... 328 Write Waveforms ..................................................... 111 Phase Buffer Segments ................................................... 219 PICDEM 1 Low Cost PICmicro Demo Board ................... 307 PICDEM 2 Low Cost PIC16CXX Demo Board ................ 307 PICDEM 3 Low Cost PIC16CXXX Demo Board .............. 308 PICSTART Plus Entry Level Development System ......... 307 Pin Functions AVDD .......................................................................... 20 AVSS .......................................................................... 20 MCLR/VPP ................................................................. 12 OSC1/CLKI ................................................................ 12 OSC2/CLKO .............................................................. 12 RA0/AN0 .................................................................... 13 RA1/AN1 .................................................................... 13 RA2/AN2/VREF- ......................................................... 13 RA3/AN3/VREF+ ........................................................ 13 RA4/T0CKI ................................................................ 13 RA5/AN4/SS/LVDIN .................................................. 13 RA6 ............................................................................ 13 RB0/INT0 ................................................................... 14 K KEELOQ Evaluation and Programming Tools ................... 308 L Lengthening a Bit Period .................................................. 221 Listen Only Mode ............................................................. 210 Loopback Mode ............................................................... 211 M Memory Organization Data Memory ............................................................. 48 Program Memory ....................................................... 41 Message Acceptance Filter .............................................. 217 Message Acceptance Filters and Masks ......................... 216 Message Reception ......................................................... 213 Message Reception Flowchart ......................................... 215 MOVFP ............................................................................ 286 MOVLB ............................................................................ 285 MOVLR .................................................................... 285, 286 MOVLW ........................................................................... 287 MOVWF ........................................................................... 287 2000 Microchip Technology Inc. Advanced Information DS30475A-page 355 PIC18CXX8 RB1/INT1 ................................................................... 14 RB2/INT2 ................................................................... 14 RB3/INT3 ................................................................... 14 RB4 ............................................................................ 14 RB5 ............................................................................ 14 RB6 ............................................................................ 14 RB7 ............................................................................ 14 RC0/T1OSO/T1CKI ................................................... 15 RC1/T1OSI ................................................................ 15 RC2/CCP1 ................................................................. 15 RC3/SCK/SCL ........................................................... 15 RC4/SDI/SDA ............................................................ 15 RC5/SDO ................................................................... 15 RC6/TX/CK ................................................................ 15 RC7/RX/DT ................................................................ 15 RD0/AD0 .................................................................... 16 RD0/PSP0 .................................................................. 16 RD1/AD1 .................................................................... 16 RD1/PSP1 .................................................................. 16 RD2/AD2 .................................................................... 16 RD2/PSP2 .................................................................. 16 RD3/AD3 .................................................................... 16 RD3/PSP3 .................................................................. 16 RD4/AD4 .................................................................... 16 RD4/PSP4 .................................................................. 16 RD5/AD5 .................................................................... 16 RD5/PSP5 .................................................................. 16 RD6/AD6 .................................................................... 16 RD6/PSP6 .................................................................. 16 RD7/AD7 .................................................................... 16 RD7/PSP7 .................................................................. 16 RE0/ALE .................................................................... 17 RE0/RD ...................................................................... 17 RE1/OE ...................................................................... 17 RE1/WR ..................................................................... 17 RE2/CS ...................................................................... 17 RE2/WRL ................................................................... 17 RE3/WRH .................................................................. 17 RE4 ............................................................................ 17 RE5 ............................................................................ 17 RE6 ............................................................................ 17 RE7/CCP2 ................................................................. 17 RF0/AN5 .................................................................... 18 RF1/AN6 .................................................................... 18 RF2/AN7 .................................................................... 18 RF3/AN8 .................................................................... 18 RF4/AN9 .................................................................... 18 RF5/AN10 .................................................................. 18 RF6/AN11 .................................................................. 18 RF7 ............................................................................ 18 RG0/CANTX1 ............................................................ 19 RG1/CANTX2 ............................................................ 19 RG2/CANRX .............................................................. 19 RG3 ............................................................................ 19 RG4 ............................................................................ 19 RH0/A16 .................................................................... 19 RH1/A17 .................................................................... 19 RH2/A18 .................................................................... 19 RH3/A19 .................................................................... 19 RH4/AN12 .................................................................. 19 RH5/AN13 .................................................................. 19 RH6/AN14 .................................................................. 19 RH7/AN15 .................................................................. 19 RJ0/AD8 ..................................................................... 20 RJ1/AD9 ..................................................................... 20 RJ2/AD10 ................................................................... 20 RJ3/AD11 ................................................................... 20 RK0 ............................................................................ 20 RK1 ............................................................................ 20 RK2 ............................................................................ 20 RK3 ............................................................................ 20 VDD ............................................................................ 20 VSS ............................................................................ 20 Pointer, FSR ...................................................................... 61 POR. See Power-on Reset PORTA Initialization ................................................................ 89 PORTA Register ........................................................ 89 RA3:RA0 and RA5 Port Pins ..................................... 89 RA4/T0CKI Pin .......................................................... 90 TRISA Register .......................................................... 89 PORTB Initialization ................................................................ 91 PORTB Register ........................................................ 91 RB0/INT Pin, External ................................................ 88 RB3:RB0 Port Pins .................................................... 91 RB7:RB4 Interrupt on Change Flag (RBIF Bit) .......... 91 RB7:RB4 Port Pins .................................................... 91 TRISB Register .......................................................... 91 PORTC Block Diagram ........................................................... 93 Initialization ................................................................ 93 PORTC Register ........................................................ 93 RC3/SCK/SCL Pin ................................................... 149 RC7/RX/DT Pin ........................................................ 169 TRISC Register .................................................. 93, 167 PORTD ............................................................................ 109 Block Diagram ........................................................... 95 Initialization ................................................................ 95 Parallel Slave Port (PSP) Function ............................ 95 PORTD Register ........................................................ 95 TRISD Register .......................................................... 95 PORTE Block Diagram ........................................................... 97 Initialization ................................................................ 97 PORTE Register ........................................................ 97 PSP Mode Select (PSPMODE Bit) .................... 95, 109 RE0/RD ................................................................... 109 RE1/WR ................................................................... 109 RE2/CS .................................................................... 109 TRISE Register .......................................................... 97 PORTF Block Diagram ........................................................... 99 Block Diagram of RF7 Pin ....................................... 100 C1OUT, C2OUT ........................................................ 99 Initialization ................................................................ 99 PORTF Register ........................................................ 99 RF6/RF3 and RF0 Pins Block Diagram ................... 100 TRISF ........................................................................ 99 PORTG Initialization .............................................................. 101 PORTG .................................................................... 101 RG0/CANTX0 Pin Block Diagram ............................ 101 RG1/CANTX1 Pin Block Diagram ............................ 102 RG2 Pin Block Diagram ........................................... 102 RG4/RG3 Pins Block Diagram ................................. 102 TRISG ...................................................................... 101 PORTH Initialization .............................................................. 104 PORTH .................................................................... 104 RH3/RH0 Pins Block Diagram ................................. 104 RH7/RH4 Pins Block Diagram ................................. 104 TRISH ...................................................................... 104 DS30475A-page 356 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 PORTJ Initialization .............................................................. 106 PORTJ ..................................................................... 106 TRISJ ....................................................................... 106 PORTJ Block Diagram ..................................................... 106 PORTK Initialization .............................................................. 108 PORTK ..................................................................... 108 TRISK ...................................................................... 108 Postscaler, WDT Assignment (PSA Bit) .............................................. 115 Rate Select (PS2:PS0 Bits) ..................................... 115 Switching Between Timer0 and WDT ...................... 115 Power-down Mode. See SLEEP Power-on Reset (POR) .............................................. 30, 251 Oscillator Start-up Timer (OST) ......................... 30, 251 Power-up Timer (PWRT) ................................... 30, 251 Time-out Sequence .................................................... 31 Time-out Sequence on Power-up ........................ 32, 33 Timing Diagram ........................................................ 325 Prescaler, Capture ........................................................... 129 Prescaler, Timer0 ............................................................. 115 Assignment (PSA Bit) .............................................. 115 Rate Select (PS2:PS0 Bits) ..................................... 115 Switching Between Timer0 and WDT ...................... 115 Prescaler, Timer1 ............................................................. 118 Prescaler, Timer2 ............................................................. 132 PRO MAT" II Universal Programmer ............................... 307 Program Counter PCL Register .............................................................. 45 PCLATH Register ...................................................... 45 Program Memory ............................................................... 41 Program Verification ........................................................ 259 Programmable ................................................................. 251 Programming Time Segments ......................................... 222 Programming, Device Instructions ................................... 261 Propagation Segment ...................................................... 219 PSPCON Register PSPMODE Bit .................................................... 95, 109 PWM (CCP Module) ........................................................ 132 Block Diagram .......................................................... 132 CCPR1H:CCPR1L Registers ................................... 132 Duty Cycle ................................................................ 132 Example Frequencies/Resolutions .......................... 133 Output Diagram ........................................................ 132 Period ....................................................................... 132 Setup for PWM Operation ........................................ 133 TMR2 to PR2 Match ........................................ 121, 132 Registers SSPSTAT ................................................................ 136 T3CON Diagram ........................................................... 123 Section ............................................................ 123 RESET ....................................................................... 29, 251 Timing Diagram ....................................................... 325 Resynchronization ........................................................... 220 RETFIE .................................................................... 291, 292 RETLW ............................................................................ 292 RETURN .......................................................................... 293 Revision History ............................................................... 349 RLCF ............................................................................... 293 RLNCF ............................................................................. 294 RRCF ............................................................................... 294 RRNCF ............................................................................ 295 S Sample Point ................................................................... 219 SCI. See USART SCK ................................................................................. 141 SDI ................................................................................... 141 SDO ................................................................................. 141 Serial Clock, SCK ............................................................ 141 Serial Communication Interface. See USART Serial Data In, SDI ........................................................... 141 Serial Data Out, SDO ...................................................... 141 Serial Peripheral Interface. See SPI Shortening a Bit Period .................................................... 221 Simplified Block Diagram of On-Chip Reset Circuit ........... 29 Slave Select Synchronization .......................................... 144 Slave Select, SS .............................................................. 141 SLEEP ............................................................. 251, 257, 296 Software Simulator (MPLAB-SIM) ................................... 306 Special Event Trigger. See Compare Special Features of the CPU ................................... 247, 251 Special Function Registers ................................................ 48 SPI Master Mode ............................................................ 143 Serial Clock ............................................................. 141 Serial Data In ........................................................... 141 Serial Data Out ........................................................ 141 Slave Select ............................................................. 141 SPI Clock ................................................................. 143 SPI Mode ................................................................. 141 SPI Module Slave Mode .............................................................. 144 Slave Select Synchronization .................................. 144 Slave Synch Timing ................................................. 144 Slave Timing with CKE = 0 ...................................... 145 Slave Timing with CKE = 1 ...................................... 145 SS .................................................................................... 141 SSP ................................................................................. 135 Block Diagram (SPI Mode) ...................................... 141 I2C Mode. See I2C SPI Mode ................................................................. 141 SPI Mode. See SPI SSPBUF .................................................................. 143 SSPCON1 ............................................................... 138 SSPCON2 ............................................................... 140 SSPSR .................................................................... 143 SSPSTAT ................................................................ 136 TMR2 Output for Clock Shift ............................ 121, 122 SSP Module SPI Master Mode ..................................................... 143 SPI Slave Mode ....................................................... 144 SSPCON1 ....................................................................... 138 SSPCON2 ....................................................................... 140 Q Q-Clock ............................................................................ 132 R RAM. See Data Memory RCSTA Register SPEN Bit .................................................................. 167 Receive Buffers ................................................................ 213 Receive Buffers Diagram ................................................. 214 Receive Interrupt .............................................................. 225 Receive Message Buffering ............................................. 213 Receiver Error Passive .................................................... 226 Receiver Overrun ............................................................. 226 Receiver Warning ............................................................ 226 Register File ....................................................................... 48 2000 Microchip Technology Inc. Advanced Information DS30475A-page 357 PIC18CXX8 SSPOV ............................................................................. 156 SSPSTAT ......................................................................... 136 SSPSTAT Register R/W Bit ............................................................. 148, 149 Stuff Error ......................................................................... 223 SUBLW ............................................................................ 297 SUBWF .................................................................... 297, 298 SUBWFB .......................................................................... 299 SWAPF ............................................................................ 300 Synchronization ................................................................ 220 Synchronization Rules ..................................................... 220 Synchronization Segment ................................................ 219 Synchronous Serial Port. See SSP Master Mode Transmit Clock Arbitration ................. 161 Repeat Start Condition ............................................ 155 Slave Synchronization ............................................. 144 Slow Rise Time .......................................................... 33 SPI Mode Timing (Master Mode) SPI Mode Master Mode Timing Diagram ......................... 143 SPI Mode Timing (Slave Mode with CKE = 0) ......... 145 SPI Mode Timing (Slave Mode with CKE = 1) ......... 145 Stop Condition Receive or Transmit ........................ 160 Time-out Sequence on Power-up .............................. 32 USART Asynchronous Master Transmission .......... 174 USART Asynchronous Reception ............................ 176 USART Synchronous Reception ............................. 179 USART Synchronous Transmission ........................ 178 Wake-up from SLEEP via Interrupt .......................... 258 Timing Diagrams and Specifications ............................... 322 A/D Conversion ........................................................ 340 Brown-out Reset (BOR) ........................................... 325 Capture/Compare/PWM (CCP) ............................... 327 CLKOUT and I/O ..................................................... 324 External Clock .......................................................... 322 I2C Bus Data ............................................................ 334 I2C Bus START/STOP Bits ...................................... 333 Oscillator Start-up Timer (OST) ............................... 325 Parallel Slave Port (PSP) ......................................... 328 Power-up Timer (PWRT) ......................................... 325 Reset ....................................................................... 325 Timer0 and Timer1 .................................................. 326 USART Synchronous Receive ( Master/Slave) ....... 338 USART Synchronous Transmission ( Master/Slave) 337 Watchdog Timer (WDT) ........................................... 325 Transmit Interrupt ............................................................ 225 Transmit Message Aborting ............................................. 211 Transmit Message Buffering ............................................ 211 Transmit Message Buffers ............................................... 211 Transmit Message flowchart ............................................ 212 Transmit Message Priority ............................................... 211 Transmitter Error Passive ................................................ 226 Transmitter Warning ........................................................ 226 TRISE Register .................................................................. 97 TSTFSZ ........................................................................... 303 TXSTA Register BRGH Bit ................................................................. 169 T TABLRD ........................................................................... 301 TABLWT ........................................................................... 302 Time Quanta .................................................................... 219 Timer Modules Timer3 Block Diagram .................................................. 124 Timer0 .............................................................................. 113 Clock Source Edge Select (T0SE Bit) ...................... 115 Clock Source Select (T0CS Bit) ............................... 115 Overflow Interrupt .................................................... 116 Prescaler. See Prescaler, Timer0 Timing Diagram ........................................................ 326 Timer1 .............................................................................. 117 Block Diagram .......................................................... 118 Oscillator .......................................................... 117, 119 Overflow Interrupt ............................................ 117, 119 Prescaler. See Prescaler, Timer1 Special Event Trigger (CCP) ............................ 119, 130 Timing Diagram ........................................................ 326 TMR1H Register ...................................................... 117 TMR1L Register ....................................................... 117 TMR3L Register ....................................................... 123 Timer2 Block Diagram .......................................................... 122 Postscaler. See Postscaler, Timer2 PR2 Register .................................................... 121, 132 Prescaler. See Prescaler, Timer2 SSP Clock Shift ................................................ 121, 122 TMR2 Register ......................................................... 121 TMR2 to PR2 Match Interrupt .................. 121, 122, 132 Timer3 .............................................................................. 123 Oscillator .......................................................... 123, 125 Overflow Interrupt ............................................ 123, 125 Special Event Trigger (CCP) .................................... 125 TMR3H Register ...................................................... 123 Timing Diagrams Acknowledge Sequence Timing ............................... 159 Baud Rate Generator with Clock Arbitration ............ 153 BRG Reset Due to SDA Collision ............................ 164 Bus Collision START Condition Timing ................................. 163 Bus Collision During a RESTART Condition (Case 1) ................................................................... 165 Bus Collision During a RESTART Condition (Case2) .................................................................... 165 Bus Collision During a START Condition (SCL = 0) 164 Bus Collision During a STOP Condition ................... 166 Bus Collision for Transmit and Acknowledge ........... 162 I2C Bus Data ............................................................ 336 I2C Master Mode First Start bit timing ...................... 154 I2C Master Mode Reception timing .......................... 158 I2C Master Mode Transmission timing ..................... 157 U Universal Synchronous Asynchronous Receiver Transmitter. See USART USART ............................................................................. 167 Asynchronous Mode ................................................ 173 Master Transmission ....................................... 174 Receive Block Diagram ................................... 175 Reception ........................................................ 176 Transmit Block Diagram .................................. 173 Baud Rate Generator (BRG) ................................... 169 Baud Rate Error, Calculating ........................... 169 Baud Rate Formula ......................................... 169 High Baud Rate Select (BRGH Bit) ................. 169 Sampling .......................................................... 169 Serial Port Enable (SPEN Bit) ................................. 167 Synchronous Master Mode ...................................... 177 Reception ........................................................ 179 Timing Diagram, Synchronous Receive .......... 338 Timing Diagram, Synchronous Transmission .. 337 Transmission ................................................... 178 Synchronous Slave Mode ........................................ 180 DS30475A-page 358 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 W Wake-up from SLEEP .............................................. 251, 257 Timing Diagram ........................................................ 258 Watchdog Timer (WDT) ........................................... 251, 255 Block Diagram .......................................................... 256 Postscaler. See Postscaler, WDT Programming Considerations .................................. 255 RC Oscillator ............................................................ 255 Time-out Period ....................................................... 255 Timing Diagram ........................................................ 325 Waveform for General Call Address Sequence ............... 150 WCOL .............................................................. 154, 156, 159 WCOL Status Flag ........................................................... 154 WWW, On-Line Support ...................................................... 7 X XORLW ............................................................................ 303 XORWF ............................................................................ 304 2000 Microchip Technology Inc. Advanced Information DS30475A-page 359 PIC18CXX8 NOTES: DS30475A-page 360 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events Trademarks: The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC and Migratable Memory are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. 001024 2000 Microchip Technology Inc. Advanced Information DS30475A-page 361 PIC18CXX8 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: RE: Technical Publications Manager Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Device: PIC18CXX8 Questions: 1. What are the best features of this document? Y N Literature Number: DS30475A FAX: (______) _________ - _________ 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30475A-page362 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 PIC18CXX8 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery refer to the factory or the listed sales office . PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) Device PIC18CXX8 , PIC18CXX8T ; VDD range 4.2V to 5.5V PIC18LCXX5(1), PIC18LCXX8T(2); VDD range 2.5V to 5.5V (1) (2) c) PIC18LC658 - I/L 301 = Industrial temp., PLCC package, Extended VDD limits, QTP pattern #301. PIC18LC858 - I/PT = Industrial temp., TQFP package, Extended VDD limits. PIC18C658 - E/L = Extended temp., PLCC package, normal VDD limits. Temperature Range I E = -40C to +85C = -40C to +125C (Industrial) (Extended) Note 1: C = Standard Voltage Range LC = Wide Voltage Range T = in tape and reel PLCC, and TQFP packages only. CL devices are UV erasable and can be programmed to any device configuration. CL devices meet the electrical requirement of each oscillator type (including LC devices). Package CL PT L = = = Windowed JCERPACK TQFP (Thin Quad Flatpack) PLCC 2: 3: Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type. Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2000 Microchip Technology Inc. Advanced Information DS30475A-page 363 PIC18CXX8 NOTES: DS30475A-page 364 Advanced Information 2000 Microchip Technology Inc. PIC18CXX8 NOTES: 2000 Microchip Technology Inc. Advanced Information DS30475A-page 365 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com ASIA/PACIFIC China - Beijing Microchip Technology Beijing Office Unit 915 New China Hong Kong Manhattan Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 ASIA/PACIFIC (continued) Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Rocky Mountain 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 China - Shanghai Microchip Technology Shanghai Office Room 701, Bldg. B Far East International Plaza No. 317 Xian Xia Road Shanghai, 200051 Tel: 86-21-6275-5700 Fax: 86-21-6275-5060 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 EUROPE Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3838 Fax: 978-692-3821 Hong Kong Microchip Asia Pacific RM 2101, Tower 2, Metroplaza 223 Hing Fong Road Kwai Fong, N.T., Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 India Microchip Technology Inc. India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 France Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Dallas 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Dayton Two Prestige Place, Suite 130 Miamisburg, OH 45342 Tel: 937-291-1654 Fax: 937-291-9175 Germany Arizona Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Japan Microchip Technology Intl. Inc. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea Tel: 82-2-554-7200 Fax: 82-2-558-5934 Los Angeles 18201 Von Karman, Suite 1090 Irvine, CA 92612 Tel: 949-263-1888 Fax: 949-263-1338 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 10/01/00 New York 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 Tel: 631-273-5305 Fax: 631-273-5335 San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. All rights reserved. (c) 2000 Microchip Technology Incorporated. Printed in the USA. 11/00 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, except as maybe explicitly expressed herein, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. DS30475A-page 366 Advanced Information 2000 Microchip Technology Inc. |
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